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Merge tag 'drm-intel-next-fixes-2015-05-29' of git://anongit.freedesktop.org/drm-intel into drm-next

Browse source 
Fixes for 4.2. Nothing too serious (given that it's still pre merge
window). With that it's off for 2 weeks of vacation for me and taking care
of 4.2 fixes for Jani.

* tag 'drm-intel-next-fixes-2015-05-29' of git://anongit.freedesktop.org/drm-intel:
  drm/i915: limit PPGTT size to 2GB in 32-bit platforms
  drm/i915: Another fbdev hack to avoid PSR on fbcon.
  drm/i915: Return the frontbuffer flip to enable intel_crtc_enable_planes.
  drm/i915: disable IPS while getting the sink CRCs
  drm/i915: Disable 12bpc hdmi for now
  drm/i915: Adjust sideband locking a bit for CHV/VLV
  drm/i915: s/dpio_lock/sb_lock/
  drm/i915: Kill intel_flush_primary_plane()
  drm/i915: Throw out WIP CHV power well definitions
  drm/i915: Use the default 600ns LDO programming sequence delay
  drm/i915: Remove unnecessary null check in execlists_context_unqueue
  drm/i915: Use spinlocks for checking when to waitboost
  drm/i915: Fix the confusing comment about the ioctl limits
  Revert "drm/i915: Force clean compilation with -Werror"
This commit is contained in:
Dave Airlie 2015-06-02 18:10:50 +10:00
commit 3e8d222f2a
24 changed files with 247 additions and 297 deletions
Download patch file Download diff file Expand all files Collapse all files

8
drivers/gpu/drm/i915/Kconfig
View file

@ -71,11 +71,3 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT
option changes the default for that module option. option changes the default for that module option.
If in doubt, say "N". If in doubt, say "N".
menu "DRM i915 Debugging"
depends on DRM_I915
source drivers/gpu/drm/i915/Kconfig.debug
endmenu

5
drivers/gpu/drm/i915/Kconfig.debug
View file

@ -1,5 +0,0 @@
config DRM_I915_WERROR
bool "Force GCC to throw an error instead of a warning when compiling"
default n
---help---
Add -Werror to the build flags for (and only for) i915.ko

2
drivers/gpu/drm/i915/Makefile
View file

@ -2,8 +2,6 @@
# Makefile for the drm device driver. This driver provides support for the # Makefile for the drm device driver. This driver provides support for the
# Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
subdir-ccflags-$(CONFIG_DRM_I915_WERROR) := -Werror
# Please keep these build lists sorted! # Please keep these build lists sorted!
# core driver code # core driver code

17
drivers/gpu/drm/i915/i915_debugfs.c
View file

@ -2300,15 +2300,6 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_file *file; struct drm_file *file;
int ret;
ret = mutex_lock_interruptible(&dev->struct_mutex);
if (ret)
return ret;
ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
if (ret)
goto unlock;
seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled); seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy); seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
@ -2319,6 +2310,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit), intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit), intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
intel_gpu_freq(dev_priv, dev_priv->rps.max_freq)); intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
spin_lock(&dev_priv->rps.client_lock);
list_for_each_entry_reverse(file, &dev->filelist, lhead) { list_for_each_entry_reverse(file, &dev->filelist, lhead) {
struct drm_i915_file_private *file_priv = file->driver_priv; struct drm_i915_file_private *file_priv = file->driver_priv;
struct task_struct *task; struct task_struct *task;
@ -2339,12 +2331,9 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
dev_priv->rps.mmioflips.boosts, dev_priv->rps.mmioflips.boosts,
list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active"); list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts); seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
spin_unlock(&dev_priv->rps.client_lock);
mutex_unlock(&dev_priv->rps.hw_lock); return 0;
unlock:
mutex_unlock(&dev->struct_mutex);
return ret;
} }
static int i915_llc(struct seq_file *m, void *data) static int i915_llc(struct seq_file *m, void *data)

2
drivers/gpu/drm/i915/i915_dma.c
View file

@ -814,7 +814,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
spin_lock_init(&dev_priv->uncore.lock); spin_lock_init(&dev_priv->uncore.lock);
spin_lock_init(&dev_priv->mm.object_stat_lock); spin_lock_init(&dev_priv->mm.object_stat_lock);
spin_lock_init(&dev_priv->mmio_flip_lock); spin_lock_init(&dev_priv->mmio_flip_lock);
mutex_init(&dev_priv->dpio_lock); mutex_init(&dev_priv->sb_lock);
mutex_init(&dev_priv->modeset_restore_lock); mutex_init(&dev_priv->modeset_restore_lock);
mutex_init(&dev_priv->csr_lock); mutex_init(&dev_priv->csr_lock);

13
drivers/gpu/drm/i915/i915_drv.h
View file

@ -1089,9 +1089,12 @@ struct intel_gen6_power_mgmt {
int last_adj; int last_adj;
enum { LOW_POWER, BETWEEN, HIGH_POWER } power; enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
spinlock_t client_lock;
struct list_head clients;
bool client_boost;
bool enabled; bool enabled;
struct delayed_work delayed_resume_work; struct delayed_work delayed_resume_work;
struct list_head clients;
unsigned boosts; unsigned boosts;
struct intel_rps_client semaphores, mmioflips; struct intel_rps_client semaphores, mmioflips;
@ -1101,7 +1104,9 @@ struct intel_gen6_power_mgmt {
/* /*
* Protects RPS/RC6 register access and PCU communication. * Protects RPS/RC6 register access and PCU communication.
* Must be taken after struct_mutex if nested. * Must be taken after struct_mutex if nested. Note that
* this lock may be held for long periods of time when
* talking to hw - so only take it when talking to hw!
*/ */
struct mutex hw_lock; struct mutex hw_lock;
}; };
@ -1661,8 +1666,8 @@ struct drm_i915_private {
/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
struct pm_qos_request pm_qos; struct pm_qos_request pm_qos;
/* DPIO indirect register protection */ /* Sideband mailbox protection */
struct mutex dpio_lock; struct mutex sb_lock;
/** Cached value of IMR to avoid reads in updating the bitfield */ /** Cached value of IMR to avoid reads in updating the bitfield */
union { union {

4
drivers/gpu/drm/i915/i915_gem.c
View file

@ -5223,9 +5223,9 @@ void i915_gem_release(struct drm_device *dev, struct drm_file *file)
spin_unlock(&file_priv->mm.lock); spin_unlock(&file_priv->mm.lock);
if (!list_empty(&file_priv->rps.link)) { if (!list_empty(&file_priv->rps.link)) {
mutex_lock(&to_i915(dev)->rps.hw_lock); spin_lock(&to_i915(dev)->rps.client_lock);
list_del(&file_priv->rps.link); list_del(&file_priv->rps.link);
mutex_unlock(&to_i915(dev)->rps.hw_lock); spin_unlock(&to_i915(dev)->rps.client_lock);
} }
} }

7
drivers/gpu/drm/i915/i915_gem_gtt.c
View file

@ -952,6 +952,13 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
ppgtt->base.start = 0; ppgtt->base.start = 0;
ppgtt->base.total = 1ULL << 32; ppgtt->base.total = 1ULL << 32;
if (IS_ENABLED(CONFIG_X86_32))
/* While we have a proliferation of size_t variables
* we cannot represent the full ppgtt size on 32bit,
* so limit it to the same size as the GGTT (currently
* 2GiB).
*/
ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
ppgtt->base.cleanup = gen8_ppgtt_cleanup; ppgtt->base.cleanup = gen8_ppgtt_cleanup;
ppgtt->base.allocate_va_range = gen8_alloc_va_range; ppgtt->base.allocate_va_range = gen8_alloc_va_range;
ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;

19
drivers/gpu/drm/i915/i915_irq.c
View file

@ -1086,8 +1086,9 @@ static void gen6_pm_rps_work(struct work_struct *work)
{ {
struct drm_i915_private *dev_priv = struct drm_i915_private *dev_priv =
container_of(work, struct drm_i915_private, rps.work); container_of(work, struct drm_i915_private, rps.work);
bool client_boost;
int new_delay, adj, min, max;
u32 pm_iir; u32 pm_iir;
int new_delay, adj;
spin_lock_irq(&dev_priv->irq_lock); spin_lock_irq(&dev_priv->irq_lock);
/* Speed up work cancelation during disabling rps interrupts. */ /* Speed up work cancelation during disabling rps interrupts. */
@ -1099,12 +1100,14 @@ static void gen6_pm_rps_work(struct work_struct *work)
dev_priv->rps.pm_iir = 0; dev_priv->rps.pm_iir = 0;
/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
client_boost = dev_priv->rps.client_boost;
dev_priv->rps.client_boost = false;
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
/* Make sure we didn't queue anything we're not going to process. */ /* Make sure we didn't queue anything we're not going to process. */
WARN_ON(pm_iir & ~dev_priv->pm_rps_events); WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
if ((pm_iir & dev_priv->pm_rps_events) == 0) if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
return; return;
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
@ -1113,7 +1116,13 @@ static void gen6_pm_rps_work(struct work_struct *work)
adj = dev_priv->rps.last_adj; adj = dev_priv->rps.last_adj;
new_delay = dev_priv->rps.cur_freq; new_delay = dev_priv->rps.cur_freq;
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { min = dev_priv->rps.min_freq_softlimit;
max = dev_priv->rps.max_freq_softlimit;
if (client_boost) {
new_delay = dev_priv->rps.max_freq_softlimit;
adj = 0;
} else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
if (adj > 0) if (adj > 0)
adj *= 2; adj *= 2;
else /* CHV needs even encode values */ else /* CHV needs even encode values */
@ -1149,9 +1158,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
* interrupt * interrupt
*/ */
new_delay += adj; new_delay += adj;
new_delay = clamp_t(int, new_delay, new_delay = clamp_t(int, new_delay, min, max);
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
intel_set_rps(dev_priv->dev, new_delay); intel_set_rps(dev_priv->dev, new_delay);

8
drivers/gpu/drm/i915/i915_reg.h
View file

@ -595,10 +595,6 @@ enum punit_power_well {
PUNIT_POWER_WELL_DPIO_RX0 = 10, PUNIT_POWER_WELL_DPIO_RX0 = 10,
PUNIT_POWER_WELL_DPIO_RX1 = 11, PUNIT_POWER_WELL_DPIO_RX1 = 11,
PUNIT_POWER_WELL_DPIO_CMN_D = 12, PUNIT_POWER_WELL_DPIO_CMN_D = 12,
/* FIXME: guesswork below */
PUNIT_POWER_WELL_DPIO_TX_D_LANES_01 = 13,
PUNIT_POWER_WELL_DPIO_TX_D_LANES_23 = 14,
PUNIT_POWER_WELL_DPIO_RX2 = 15,
PUNIT_POWER_WELL_NUM, PUNIT_POWER_WELL_NUM,
}; };
@ -2145,6 +2141,10 @@ enum skl_disp_power_wells {
#define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240) #define DPIO_PHY_STATUS (VLV_DISPLAY_BASE + 0x6240)
#define DPLL_PORTD_READY_MASK (0xf) #define DPLL_PORTD_READY_MASK (0xf)
#define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100) #define DISPLAY_PHY_CONTROL (VLV_DISPLAY_BASE + 0x60100)
#define PHY_LDO_DELAY_0NS 0x0
#define PHY_LDO_DELAY_200NS 0x1
#define PHY_LDO_DELAY_600NS 0x2
#define PHY_LDO_SEQ_DELAY(delay, phy) ((delay) << (2*(phy)+23))
#define PHY_CH_SU_PSR 0x1 #define PHY_CH_SU_PSR 0x1
#define PHY_CH_DEEP_PSR 0x7 #define PHY_CH_DEEP_PSR 0x7
#define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2)) #define PHY_CH_POWER_MODE(mode, phy, ch) ((mode) << (6*(phy)+3*(ch)+2))

83
drivers/gpu/drm/i915/intel_display.c
View file

@ -1140,9 +1140,9 @@ static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
u32 val; u32 val;
bool cur_state; bool cur_state;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
cur_state = val & DSI_PLL_VCO_EN; cur_state = val & DSI_PLL_VCO_EN;
I915_STATE_WARN(cur_state != state, I915_STATE_WARN(cur_state != state,
@ -1661,13 +1661,15 @@ static void chv_enable_pll(struct intel_crtc *crtc,
BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* Enable back the 10bit clock to display controller */ /* Enable back the 10bit clock to display controller */
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
tmp |= DPIO_DCLKP_EN; tmp |= DPIO_DCLKP_EN;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
mutex_unlock(&dev_priv->sb_lock);
/* /*
* Need to wait > 100ns between dclkp clock enable bit and PLL enable. * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
*/ */
@ -1683,8 +1685,6 @@ static void chv_enable_pll(struct intel_crtc *crtc,
/* not sure when this should be written */ /* not sure when this should be written */
I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
POSTING_READ(DPLL_MD(pipe)); POSTING_READ(DPLL_MD(pipe));
mutex_unlock(&dev_priv->dpio_lock);
} }
static int intel_num_dvo_pipes(struct drm_device *dev) static int intel_num_dvo_pipes(struct drm_device *dev)
@ -1826,7 +1826,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
I915_WRITE(DPLL(pipe), val); I915_WRITE(DPLL(pipe), val);
POSTING_READ(DPLL(pipe)); POSTING_READ(DPLL(pipe));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* Disable 10bit clock to display controller */ /* Disable 10bit clock to display controller */
val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
@ -1844,7 +1844,7 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
} }
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
void vlv_wait_port_ready(struct drm_i915_private *dev_priv, void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
@ -2210,20 +2210,6 @@ static void intel_disable_pipe(struct intel_crtc *crtc)
intel_wait_for_pipe_off(crtc); intel_wait_for_pipe_off(crtc);
} }
/*
* Plane regs are double buffered, going from enabled->disabled needs a
* trigger in order to latch. The display address reg provides this.
*/
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane)
{
struct drm_device *dev = dev_priv->dev;
u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
I915_WRITE(reg, I915_READ(reg));
POSTING_READ(reg);
}
/** /**
* intel_enable_primary_hw_plane - enable the primary plane on a given pipe * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
* @plane: plane to be enabled * @plane: plane to be enabled
@ -3953,7 +3939,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
u32 divsel, phaseinc, auxdiv, phasedir = 0; u32 divsel, phaseinc, auxdiv, phasedir = 0;
u32 temp; u32 temp;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* It is necessary to ungate the pixclk gate prior to programming /* It is necessary to ungate the pixclk gate prior to programming
* the divisors, and gate it back when it is done. * the divisors, and gate it back when it is done.
@ -4030,7 +4016,7 @@ static void lpt_program_iclkip(struct drm_crtc *crtc)
I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
@ -4842,11 +4828,22 @@ intel_pre_disable_primary(struct drm_crtc *crtc)
static void intel_crtc_enable_planes(struct drm_crtc *crtc) static void intel_crtc_enable_planes(struct drm_crtc *crtc)
{ {
struct drm_device *dev = crtc->dev;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
intel_enable_primary_hw_plane(crtc->primary, crtc); intel_enable_primary_hw_plane(crtc->primary, crtc);
intel_enable_sprite_planes(crtc); intel_enable_sprite_planes(crtc);
intel_crtc_update_cursor(crtc, true); intel_crtc_update_cursor(crtc, true);
intel_post_enable_primary(crtc); intel_post_enable_primary(crtc);
/*
* FIXME: Once we grow proper nuclear flip support out of this we need
* to compute the mask of flip planes precisely. For the time being
* consider this a flip to a NULL plane.
*/
intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
} }
static void intel_crtc_disable_planes(struct drm_crtc *crtc) static void intel_crtc_disable_planes(struct drm_crtc *crtc)
@ -5742,10 +5739,10 @@ static int valleyview_get_vco(struct drm_i915_private *dev_priv)
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
/* Obtain SKU information */ /* Obtain SKU information */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK; CCK_FUSE_HPLL_FREQ_MASK;
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
return vco_freq[hpll_freq] * 1000; return vco_freq[hpll_freq] * 1000;
} }
@ -5794,12 +5791,13 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
} }
mutex_unlock(&dev_priv->rps.hw_lock); mutex_unlock(&dev_priv->rps.hw_lock);
mutex_lock(&dev_priv->sb_lock);
if (cdclk == 400000) { if (cdclk == 400000) {
u32 divider; u32 divider;
divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
mutex_lock(&dev_priv->dpio_lock);
/* adjust cdclk divider */ /* adjust cdclk divider */
val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
val &= ~DISPLAY_FREQUENCY_VALUES; val &= ~DISPLAY_FREQUENCY_VALUES;
@ -5810,10 +5808,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
50)) 50))
DRM_ERROR("timed out waiting for CDclk change\n"); DRM_ERROR("timed out waiting for CDclk change\n");
mutex_unlock(&dev_priv->dpio_lock);
} }
mutex_lock(&dev_priv->dpio_lock);
/* adjust self-refresh exit latency value */ /* adjust self-refresh exit latency value */
val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
val &= ~0x7f; val &= ~0x7f;
@ -5827,7 +5823,8 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
else else
val |= 3000 / 250; /* 3.0 usec */ val |= 3000 / 250; /* 3.0 usec */
vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
mutex_unlock(&dev_priv->dpio_lock);
mutex_unlock(&dev_priv->sb_lock);
vlv_update_cdclk(dev); vlv_update_cdclk(dev);
} }
@ -6755,9 +6752,9 @@ static int valleyview_get_display_clock_speed(struct drm_device *dev)
if (dev_priv->hpll_freq == 0) if (dev_priv->hpll_freq == 0)
dev_priv->hpll_freq = valleyview_get_vco(dev_priv); dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
divider = val & DISPLAY_FREQUENCY_VALUES; divider = val & DISPLAY_FREQUENCY_VALUES;
@ -7099,7 +7096,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
u32 bestn, bestm1, bestm2, bestp1, bestp2; u32 bestn, bestm1, bestm2, bestp1, bestp2;
u32 coreclk, reg_val; u32 coreclk, reg_val;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
bestn = pipe_config->dpll.n; bestn = pipe_config->dpll.n;
bestm1 = pipe_config->dpll.m1; bestm1 = pipe_config->dpll.m1;
@ -7177,7 +7174,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void chv_update_pll(struct intel_crtc *crtc, static void chv_update_pll(struct intel_crtc *crtc,
@ -7222,7 +7219,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
I915_WRITE(dpll_reg, I915_WRITE(dpll_reg,
pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* p1 and p2 divider */ /* p1 and p2 divider */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
@ -7295,7 +7292,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
DPIO_AFC_RECAL); DPIO_AFC_RECAL);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
/** /**
@ -7796,9 +7793,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
return; return;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
clock.m2 = mdiv & DPIO_M2DIV_MASK; clock.m2 = mdiv & DPIO_M2DIV_MASK;
@ -7892,12 +7889,12 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
int refclk = 100000; int refclk = 100000;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
@ -8263,7 +8260,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
with_fdi, "LP PCH doesn't have FDI\n")) with_fdi, "LP PCH doesn't have FDI\n"))
with_fdi = false; with_fdi = false;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
tmp &= ~SBI_SSCCTL_DISABLE; tmp &= ~SBI_SSCCTL_DISABLE;
@ -8289,7 +8286,7 @@ static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
/* Sequence to disable CLKOUT_DP */ /* Sequence to disable CLKOUT_DP */
@ -8298,7 +8295,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
uint32_t reg, tmp; uint32_t reg, tmp;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
SBI_GEN0 : SBI_DBUFF0; SBI_GEN0 : SBI_DBUFF0;
@ -8317,7 +8314,7 @@ static void lpt_disable_clkout_dp(struct drm_device *dev)
intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
} }
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void lpt_init_pch_refclk(struct drm_device *dev) static void lpt_init_pch_refclk(struct drm_device *dev)

94
drivers/gpu/drm/i915/intel_dp.c
View file

@ -2355,7 +2355,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
intel_dp_link_down(intel_dp); intel_dp_link_down(intel_dp);
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* Propagate soft reset to data lane reset */ /* Propagate soft reset to data lane reset */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
@ -2374,7 +2374,7 @@ static void chv_post_disable_dp(struct intel_encoder *encoder)
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void static void
@ -2671,7 +2671,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
u32 val; u32 val;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
val = 0; val = 0;
@ -2684,7 +2684,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
intel_enable_dp(encoder); intel_enable_dp(encoder);
} }
@ -2702,7 +2702,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
intel_dp_prepare(encoder); intel_dp_prepare(encoder);
/* Program Tx lane resets to default */ /* Program Tx lane resets to default */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE2_RESET |
DPIO_PCS_TX_LANE1_RESET); DPIO_PCS_TX_LANE1_RESET);
@ -2716,7 +2716,7 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void chv_pre_enable_dp(struct intel_encoder *encoder) static void chv_pre_enable_dp(struct intel_encoder *encoder)
@ -2732,7 +2732,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
int data, i, stagger; int data, i, stagger;
u32 val; u32 val;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* allow hardware to manage TX FIFO reset source */ /* allow hardware to manage TX FIFO reset source */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
@ -2802,7 +2802,7 @@ static void chv_pre_enable_dp(struct intel_encoder *encoder)
DPIO_TX1_STAGGER_MULT(7) | DPIO_TX1_STAGGER_MULT(7) |
DPIO_TX2_STAGGER_MULT(5)); DPIO_TX2_STAGGER_MULT(5));
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
intel_enable_dp(encoder); intel_enable_dp(encoder);
} }
@ -2820,7 +2820,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
intel_dp_prepare(encoder); intel_dp_prepare(encoder);
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* program left/right clock distribution */ /* program left/right clock distribution */
if (pipe != PIPE_B) { if (pipe != PIPE_B) {
@ -2870,7 +2870,7 @@ static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
val |= CHV_CMN_USEDCLKCHANNEL; val |= CHV_CMN_USEDCLKCHANNEL;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
/* /*
@ -3095,7 +3095,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
return 0; return 0;
} }
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
@ -3104,7 +3104,7 @@ static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
return 0; return 0;
} }
@ -3191,7 +3191,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
return 0; return 0;
} }
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* Clear calc init */ /* Clear calc init */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
@ -3278,7 +3278,7 @@ static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
val |= DPIO_LRC_BYPASS; val |= DPIO_LRC_BYPASS;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
return 0; return 0;
} }
@ -4041,46 +4041,70 @@ int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
u8 buf; u8 buf;
int test_crc_count; int test_crc_count;
int attempts = 6; int attempts = 6;
int ret = 0;
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) hsw_disable_ips(intel_crtc);
return -EIO;
if (!(buf & DP_TEST_CRC_SUPPORTED)) if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
return -ENOTTY; ret = -EIO;
goto out;
}
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) if (!(buf & DP_TEST_CRC_SUPPORTED)) {
return -EIO; ret = -ENOTTY;
goto out;
}
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
ret = -EIO;
goto out;
}
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
buf | DP_TEST_SINK_START) < 0) buf | DP_TEST_SINK_START) < 0) {
return -EIO; ret = -EIO;
goto out;
}
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0) {
ret = -EIO;
goto out;
}
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
return -EIO;
test_crc_count = buf & DP_TEST_COUNT_MASK; test_crc_count = buf & DP_TEST_COUNT_MASK;
do { do {
if (drm_dp_dpcd_readb(&intel_dp->aux, if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_TEST_SINK_MISC, &buf) < 0) DP_TEST_SINK_MISC, &buf) < 0) {
return -EIO; ret = -EIO;
goto out;
}
intel_wait_for_vblank(dev, intel_crtc->pipe); intel_wait_for_vblank(dev, intel_crtc->pipe);
} while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count); } while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);
if (attempts == 0) { if (attempts == 0) {
DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n"); DRM_DEBUG_KMS("Panel is unable to calculate CRC after 6 vblanks\n");
return -ETIMEDOUT; ret = -ETIMEDOUT;
goto out;
} }
if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
return -EIO; ret = -EIO;
goto out;
}
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
return -EIO; ret = -EIO;
goto out;
}
if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
buf & ~DP_TEST_SINK_START) < 0) buf & ~DP_TEST_SINK_START) < 0) {
return -EIO; ret = -EIO;
goto out;
return 0; }
out:
hsw_enable_ips(intel_crtc);
return ret;
} }
static bool static bool

2
drivers/gpu/drm/i915/intel_drv.h
View file

@ -1383,8 +1383,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
/* intel_sprite.c */ /* intel_sprite.c */
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane);
int intel_plane_restore(struct drm_plane *plane); int intel_plane_restore(struct drm_plane *plane);
int intel_sprite_set_colorkey(struct drm_device *dev, void *data, int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);

8
drivers/gpu/drm/i915/intel_dsi.c
View file

@ -239,7 +239,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
static void band_gap_reset(struct drm_i915_private *dev_priv) static void band_gap_reset(struct drm_i915_private *dev_priv)
{ {
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_flisdsi_write(dev_priv, 0x08, 0x0001); vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
@ -248,7 +248,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
vlv_flisdsi_write(dev_priv, 0x08, 0x0000); vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static inline bool is_vid_mode(struct intel_dsi *intel_dsi) static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
@ -346,11 +346,11 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* program rcomp for compliance, reduce from 50 ohms to 45 ohms /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
* needed everytime after power gate */ * needed everytime after power gate */
vlv_flisdsi_write(dev_priv, 0x04, 0x0004); vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
/* bandgap reset is needed after everytime we do power gate */ /* bandgap reset is needed after everytime we do power gate */
band_gap_reset(dev_priv); band_gap_reset(dev_priv);

4
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
View file

@ -212,7 +212,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
function = gtable[gpio].function_reg; function = gtable[gpio].function_reg;
pad = gtable[gpio].pad_reg; pad = gtable[gpio].pad_reg;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
if (!gtable[gpio].init) { if (!gtable[gpio].init) {
/* program the function */ /* program the function */
/* FIXME: remove constant below */ /* FIXME: remove constant below */
@ -224,7 +224,7 @@ static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data)
/* pull up/down */ /* pull up/down */
vlv_gpio_nc_write(dev_priv, pad, val); vlv_gpio_nc_write(dev_priv, pad, val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
return data; return data;
} }

14
drivers/gpu/drm/i915/intel_dsi_pll.c
View file

@ -244,7 +244,7 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_configure_dsi_pll(encoder); vlv_configure_dsi_pll(encoder);
@ -258,11 +258,11 @@ void vlv_enable_dsi_pll(struct intel_encoder *encoder)
if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
DSI_PLL_LOCK, 20)) { DSI_PLL_LOCK, 20)) {
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
DRM_ERROR("DSI PLL lock failed\n"); DRM_ERROR("DSI PLL lock failed\n");
return; return;
} }
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
DRM_DEBUG_KMS("DSI PLL locked\n"); DRM_DEBUG_KMS("DSI PLL locked\n");
} }
@ -274,14 +274,14 @@ void vlv_disable_dsi_pll(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
tmp &= ~DSI_PLL_VCO_EN; tmp &= ~DSI_PLL_VCO_EN;
tmp |= DSI_PLL_LDO_GATE; tmp |= DSI_PLL_LDO_GATE;
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp); vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void assert_bpp_mismatch(int pixel_format, int pipe_bpp) static void assert_bpp_mismatch(int pixel_format, int pipe_bpp)
@ -319,10 +319,10 @@ u32 vlv_get_dsi_pclk(struct intel_encoder *encoder, int pipe_bpp)
DRM_DEBUG_KMS("\n"); DRM_DEBUG_KMS("\n");
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER); pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
/* mask out other bits and extract the P1 divisor */ /* mask out other bits and extract the P1 divisor */
pll_ctl &= DSI_PLL_P1_POST_DIV_MASK; pll_ctl &= DSI_PLL_P1_POST_DIV_MASK;

28
drivers/gpu/drm/i915/intel_fbdev.c
View file

@ -96,6 +96,32 @@ static int intel_fbdev_blank(int blank, struct fb_info *info)
return ret; return ret;
} }
static int intel_fbdev_pan_display(struct fb_var_screeninfo *var,
struct fb_info *info)
{
struct drm_fb_helper *fb_helper = info->par;
struct intel_fbdev *ifbdev =
container_of(fb_helper, struct intel_fbdev, helper);
int ret;
ret = drm_fb_helper_pan_display(var, info);
if (ret == 0) {
/*
* FIXME: fbdev presumes that all callbacks also work from
* atomic contexts and relies on that for emergency oops
* printing. KMS totally doesn't do that and the locking here is
* by far not the only place this goes wrong. Ignore this for
* now until we solve this for real.
*/
mutex_lock(&fb_helper->dev->struct_mutex);
intel_fb_obj_invalidate(ifbdev->fb->obj, NULL, ORIGIN_GTT);
mutex_unlock(&fb_helper->dev->struct_mutex);
}
return ret;
}
static struct fb_ops intelfb_ops = { static struct fb_ops intelfb_ops = {
.owner = THIS_MODULE, .owner = THIS_MODULE,
.fb_check_var = drm_fb_helper_check_var, .fb_check_var = drm_fb_helper_check_var,
@ -103,7 +129,7 @@ static struct fb_ops intelfb_ops = {
.fb_fillrect = cfb_fillrect, .fb_fillrect = cfb_fillrect,
.fb_copyarea = cfb_copyarea, .fb_copyarea = cfb_copyarea,
.fb_imageblit = cfb_imageblit, .fb_imageblit = cfb_imageblit,
.fb_pan_display = drm_fb_helper_pan_display, .fb_pan_display = intel_fbdev_pan_display,
.fb_blank = intel_fbdev_blank, .fb_blank = intel_fbdev_blank,
.fb_setcmap = drm_fb_helper_setcmap, .fb_setcmap = drm_fb_helper_setcmap,
.fb_debug_enter = drm_fb_helper_debug_enter, .fb_debug_enter = drm_fb_helper_debug_enter,

27
drivers/gpu/drm/i915/intel_hdmi.c
View file

@ -1036,7 +1036,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
*/ */
if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
clock_12bpc <= portclock_limit && clock_12bpc <= portclock_limit &&
hdmi_12bpc_possible(pipe_config)) { hdmi_12bpc_possible(pipe_config) &&
0 /* FIXME 12bpc support totally broken */) {
DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
desired_bpp = 12*3; desired_bpp = 12*3;
@ -1293,7 +1294,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
u32 val; u32 val;
/* Enable clock channels for this port */ /* Enable clock channels for this port */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
val = 0; val = 0;
if (pipe) if (pipe)
@ -1316,7 +1317,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
/* Program lane clock */ /* Program lane clock */
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
intel_hdmi->set_infoframes(&encoder->base, intel_hdmi->set_infoframes(&encoder->base,
intel_crtc->config->has_hdmi_sink, intel_crtc->config->has_hdmi_sink,
@ -1340,7 +1341,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
intel_hdmi_prepare(encoder); intel_hdmi_prepare(encoder);
/* Program Tx lane resets to default */ /* Program Tx lane resets to default */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE2_RESET |
DPIO_PCS_TX_LANE1_RESET); DPIO_PCS_TX_LANE1_RESET);
@ -1357,7 +1358,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
@ -1373,7 +1374,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
intel_hdmi_prepare(encoder); intel_hdmi_prepare(encoder);
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* program left/right clock distribution */ /* program left/right clock distribution */
if (pipe != PIPE_B) { if (pipe != PIPE_B) {
@ -1423,7 +1424,7 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
val |= CHV_CMN_USEDCLKCHANNEL; val |= CHV_CMN_USEDCLKCHANNEL;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void vlv_hdmi_post_disable(struct intel_encoder *encoder) static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
@ -1436,10 +1437,10 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
int pipe = intel_crtc->pipe; int pipe = intel_crtc->pipe;
/* Reset lanes to avoid HDMI flicker (VLV w/a) */ /* Reset lanes to avoid HDMI flicker (VLV w/a) */
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void chv_hdmi_post_disable(struct intel_encoder *encoder) static void chv_hdmi_post_disable(struct intel_encoder *encoder)
@ -1453,7 +1454,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
u32 val; u32 val;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* Propagate soft reset to data lane reset */ /* Propagate soft reset to data lane reset */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
@ -1472,7 +1473,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder)
val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
static void chv_hdmi_pre_enable(struct intel_encoder *encoder) static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
@ -1490,7 +1491,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
int data, i, stagger; int data, i, stagger;
u32 val; u32 val;
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
/* allow hardware to manage TX FIFO reset source */ /* allow hardware to manage TX FIFO reset source */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
@ -1633,7 +1634,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
val |= DPIO_LRC_BYPASS; val |= DPIO_LRC_BYPASS;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
intel_hdmi->set_infoframes(&encoder->base, intel_hdmi->set_infoframes(&encoder->base,
intel_crtc->config->has_hdmi_sink, intel_crtc->config->has_hdmi_sink,

2
drivers/gpu/drm/i915/intel_lrc.c
View file

@ -427,7 +427,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *ring)
* WaIdleLiteRestore: make sure we never cause a lite * WaIdleLiteRestore: make sure we never cause a lite
* restore with HEAD==TAIL * restore with HEAD==TAIL
*/ */
if (req0 && req0->elsp_submitted) { if (req0->elsp_submitted) {
/* /*
* Apply the wa NOOPS to prevent ring:HEAD == req:TAIL * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL
* as we resubmit the request. See gen8_emit_request() * as we resubmit the request. See gen8_emit_request()

41
drivers/gpu/drm/i915/intel_pm.c
View file

@ -4143,17 +4143,25 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
dev_priv->rps.last_adj = 0; dev_priv->rps.last_adj = 0;
I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
} }
mutex_unlock(&dev_priv->rps.hw_lock);
spin_lock(&dev_priv->rps.client_lock);
while (!list_empty(&dev_priv->rps.clients)) while (!list_empty(&dev_priv->rps.clients))
list_del_init(dev_priv->rps.clients.next); list_del_init(dev_priv->rps.clients.next);
mutex_unlock(&dev_priv->rps.hw_lock); spin_unlock(&dev_priv->rps.client_lock);
} }
void gen6_rps_boost(struct drm_i915_private *dev_priv, void gen6_rps_boost(struct drm_i915_private *dev_priv,
struct intel_rps_client *rps, struct intel_rps_client *rps,
unsigned long submitted) unsigned long submitted)
{ {
u32 val; /* This is intentionally racy! We peek at the state here, then
* validate inside the RPS worker.
*/
if (!(dev_priv->mm.busy &&
dev_priv->rps.enabled &&
dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
return;
/* Force a RPS boost (and don't count it against the client) if /* Force a RPS boost (and don't count it against the client) if
* the GPU is severely congested. * the GPU is severely congested.
@ -4161,14 +4169,14 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES)) if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
rps = NULL; rps = NULL;
mutex_lock(&dev_priv->rps.hw_lock); spin_lock(&dev_priv->rps.client_lock);
val = dev_priv->rps.max_freq_softlimit; if (rps == NULL || list_empty(&rps->link)) {
if (dev_priv->rps.enabled && spin_lock_irq(&dev_priv->irq_lock);
dev_priv->mm.busy && if (dev_priv->rps.interrupts_enabled) {
dev_priv->rps.cur_freq < val && dev_priv->rps.client_boost = true;
(rps == NULL || list_empty(&rps->link))) { queue_work(dev_priv->wq, &dev_priv->rps.work);
intel_set_rps(dev_priv->dev, val); }
dev_priv->rps.last_adj = 0; spin_unlock_irq(&dev_priv->irq_lock);
if (rps != NULL) { if (rps != NULL) {
list_add(&rps->link, &dev_priv->rps.clients); list_add(&rps->link, &dev_priv->rps.clients);
@ -4176,7 +4184,7 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv,
} else } else
dev_priv->rps.boosts++; dev_priv->rps.boosts++;
} }
mutex_unlock(&dev_priv->rps.hw_lock); spin_unlock(&dev_priv->rps.client_lock);
} }
void intel_set_rps(struct drm_device *dev, u8 val) void intel_set_rps(struct drm_device *dev, u8 val)
@ -4956,9 +4964,9 @@ static void cherryview_init_gt_powersave(struct drm_device *dev)
mutex_lock(&dev_priv->rps.hw_lock); mutex_lock(&dev_priv->rps.hw_lock);
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
val = vlv_cck_read(dev_priv, CCK_FUSE_REG); val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
switch ((val >> 2) & 0x7) { switch ((val >> 2) & 0x7) {
case 0: case 0:
@ -5878,13 +5886,15 @@ static void ibx_init_clock_gating(struct drm_device *dev)
static void g4x_disable_trickle_feed(struct drm_device *dev) static void g4x_disable_trickle_feed(struct drm_device *dev)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int pipe; enum pipe pipe;
for_each_pipe(dev_priv, pipe) { for_each_pipe(dev_priv, pipe) {
I915_WRITE(DSPCNTR(pipe), I915_WRITE(DSPCNTR(pipe),
I915_READ(DSPCNTR(pipe)) | I915_READ(DSPCNTR(pipe)) |
DISPPLANE_TRICKLE_FEED_DISABLE); DISPPLANE_TRICKLE_FEED_DISABLE);
intel_flush_primary_plane(dev_priv, pipe);
I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
POSTING_READ(DSPSURF(pipe));
} }
} }
@ -6913,6 +6923,7 @@ void intel_pm_setup(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
mutex_init(&dev_priv->rps.hw_lock); mutex_init(&dev_priv->rps.hw_lock);
spin_lock_init(&dev_priv->rps.client_lock);
INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
intel_gen6_powersave_work); intel_gen6_powersave_work);

100
drivers/gpu/drm/i915/intel_runtime_pm.c
View file

@ -1233,18 +1233,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_C) | \ BIT(POWER_DOMAIN_AUX_C) | \
BIT(POWER_DOMAIN_INIT)) BIT(POWER_DOMAIN_INIT))
#define CHV_PIPE_A_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PIPE_A) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_PIPE_B_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PIPE_B) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_PIPE_C_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PIPE_C) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
@ -1260,17 +1248,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT(POWER_DOMAIN_AUX_D) | \ BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER_DOMAIN_INIT)) BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER_DOMAIN_INIT))
#define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \
BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
BIT(POWER_DOMAIN_AUX_D) | \
BIT(POWER_DOMAIN_INIT))
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_always_on_power_well_noop, .sync_hw = i9xx_always_on_power_well_noop,
.enable = i9xx_always_on_power_well_noop, .enable = i9xx_always_on_power_well_noop,
@ -1428,40 +1405,17 @@ static struct i915_power_well chv_power_wells[] = {
.domains = VLV_ALWAYS_ON_POWER_DOMAINS, .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
.ops = &i9xx_always_on_power_well_ops, .ops = &i9xx_always_on_power_well_ops,
}, },
#if 0
{ {
.name = "display", .name = "display",
.domains = VLV_DISPLAY_POWER_DOMAINS,
.data = PUNIT_POWER_WELL_DISP2D,
.ops = &vlv_display_power_well_ops,
},
#endif
{
.name = "pipe-a",
/* /*
* FIXME: pipe A power well seems to be the new disp2d well. * Pipe A power well is the new disp2d well. Pipe B and C
* At least all registers seem to be housed there. Figure * power wells don't actually exist. Pipe A power well is
* out if this a a temporary situation in pre-production * required for any pipe to work.
* hardware or a permanent state of affairs.
*/ */
.domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, .domains = VLV_DISPLAY_POWER_DOMAINS,
.data = PIPE_A, .data = PIPE_A,
.ops = &chv_pipe_power_well_ops, .ops = &chv_pipe_power_well_ops,
}, },
#if 0
{
.name = "pipe-b",
.domains = CHV_PIPE_B_POWER_DOMAINS,
.data = PIPE_B,
.ops = &chv_pipe_power_well_ops,
},
{
.name = "pipe-c",
.domains = CHV_PIPE_C_POWER_DOMAINS,
.data = PIPE_C,
.ops = &chv_pipe_power_well_ops,
},
#endif
{ {
.name = "dpio-common-bc", .name = "dpio-common-bc",
.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
@ -1474,50 +1428,6 @@ static struct i915_power_well chv_power_wells[] = {
.data = PUNIT_POWER_WELL_DPIO_CMN_D, .data = PUNIT_POWER_WELL_DPIO_CMN_D,
.ops = &chv_dpio_cmn_power_well_ops, .ops = &chv_dpio_cmn_power_well_ops,
}, },
#if 0
{
.name = "dpio-tx-b-01",
.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
},
{
.name = "dpio-tx-b-23",
.domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
},
{
.name = "dpio-tx-c-01",
.domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
},
{
.name = "dpio-tx-c-23",
.domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
},
{
.name = "dpio-tx-d-01",
.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01,
},
{
.name = "dpio-tx-d-23",
.domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS |
CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS,
.ops = &vlv_dpio_power_well_ops,
.data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23,
},
#endif
}; };
static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
@ -1724,6 +1634,8 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
* value. * value.
*/ */
dev_priv->chv_phy_control = dev_priv->chv_phy_control =
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH0) |
PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) | PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY0, DPIO_CH1) |
PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0); PHY_CH_POWER_MODE(PHY_CH_SU_PSR, DPIO_PHY1, DPIO_CH0);

18
drivers/gpu/drm/i915/intel_sideband.c
View file

@ -49,7 +49,7 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
(port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
(bar << IOSF_BAR_SHIFT); (bar << IOSF_BAR_SHIFT);
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n", DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
@ -81,10 +81,10 @@ u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRRDDA_NP, addr, &val); SB_CRRDDA_NP, addr, &val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
return val; return val;
} }
@ -93,10 +93,10 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
{ {
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT, vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRWRDA_NP, addr, &val); SB_CRWRDA_NP, addr, &val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
} }
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg) u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
@ -121,10 +121,10 @@ u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
mutex_lock(&dev_priv->dpio_lock); mutex_lock(&dev_priv->sb_lock);
vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC, vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
SB_CRRDDA_NP, addr, &val); SB_CRRDDA_NP, addr, &val);
mutex_unlock(&dev_priv->dpio_lock); mutex_unlock(&dev_priv->sb_lock);
return val; return val;
} }
@ -213,7 +213,7 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
enum intel_sbi_destination destination) enum intel_sbi_destination destination)
{ {
u32 value = 0; u32 value = 0;
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
100)) { 100)) {
@ -243,7 +243,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
{ {
u32 tmp; u32 tmp;
WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
100)) { 100)) {

30
drivers/gpu/drm/i915/intel_sprite.c
View file

@ -282,7 +282,6 @@ skl_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
I915_WRITE(PLANE_CTL(pipe, plane), 0); I915_WRITE(PLANE_CTL(pipe, plane), 0);
/* Activate double buffered register update */
I915_WRITE(PLANE_SURF(pipe, plane), 0); I915_WRITE(PLANE_SURF(pipe, plane), 0);
POSTING_READ(PLANE_SURF(pipe, plane)); POSTING_READ(PLANE_SURF(pipe, plane));
@ -339,7 +338,6 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
struct drm_device *dev = dplane->dev; struct drm_device *dev = dplane->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(dplane); struct intel_plane *intel_plane = to_intel_plane(dplane);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
int plane = intel_plane->plane; int plane = intel_plane->plane;
@ -453,8 +451,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
I915_WRITE(SPCNTR(pipe, plane), sprctl); I915_WRITE(SPCNTR(pipe, plane), sprctl);
I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) + I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
sprsurf_offset); sprsurf_offset);
POSTING_READ(SPSURF(pipe, plane));
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
} }
static void static void
@ -463,21 +460,17 @@ vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc, bool force)
struct drm_device *dev = dplane->dev; struct drm_device *dev = dplane->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(dplane); struct intel_plane *intel_plane = to_intel_plane(dplane);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
int plane = intel_plane->plane; int plane = intel_plane->plane;
I915_WRITE(SPCNTR(pipe, plane), 0); I915_WRITE(SPCNTR(pipe, plane), 0);
/* Activate double buffered register update */
I915_WRITE(SPSURF(pipe, plane), 0); I915_WRITE(SPSURF(pipe, plane), 0);
POSTING_READ(SPSURF(pipe, plane));
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false); intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
} }
static void static void
ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
struct drm_framebuffer *fb, struct drm_framebuffer *fb,
@ -489,7 +482,6 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
struct drm_device *dev = plane->dev; struct drm_device *dev = plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane); struct intel_plane *intel_plane = to_intel_plane(plane);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *obj = intel_fb_obj(fb);
enum pipe pipe = intel_plane->pipe; enum pipe pipe = intel_plane->pipe;
u32 sprctl, sprscale = 0; u32 sprctl, sprscale = 0;
@ -599,8 +591,7 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
I915_WRITE(SPRCTL(pipe), sprctl); I915_WRITE(SPRCTL(pipe), sprctl);
I915_WRITE(SPRSURF(pipe), I915_WRITE(SPRSURF(pipe),
i915_gem_obj_ggtt_offset(obj) + sprsurf_offset); i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
POSTING_READ(SPRSURF(pipe));
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
} }
static void static void
@ -609,17 +600,15 @@ ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
struct drm_device *dev = plane->dev; struct drm_device *dev = plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane); struct intel_plane *intel_plane = to_intel_plane(plane);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
/* Can't leave the scaler enabled... */ /* Can't leave the scaler enabled... */
if (intel_plane->can_scale) if (intel_plane->can_scale)
I915_WRITE(SPRSCALE(pipe), 0); I915_WRITE(SPRSCALE(pipe), 0);
/* Activate double buffered register update */
I915_WRITE(SPRSURF(pipe), 0);
intel_flush_primary_plane(dev_priv, intel_crtc->plane); I915_WRITE(SPRSURF(pipe), 0);
POSTING_READ(SPRSURF(pipe));
} }
static void static void
@ -633,7 +622,6 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
struct drm_device *dev = plane->dev; struct drm_device *dev = plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane); struct intel_plane *intel_plane = to_intel_plane(plane);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *obj = intel_fb_obj(fb);
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
unsigned long dvssurf_offset, linear_offset; unsigned long dvssurf_offset, linear_offset;
@ -730,8 +718,7 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
I915_WRITE(DVSCNTR(pipe), dvscntr); I915_WRITE(DVSCNTR(pipe), dvscntr);
I915_WRITE(DVSSURF(pipe), I915_WRITE(DVSSURF(pipe),
i915_gem_obj_ggtt_offset(obj) + dvssurf_offset); i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
POSTING_READ(DVSSURF(pipe));
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
} }
static void static void
@ -740,17 +727,14 @@ ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc, bool force)
struct drm_device *dev = plane->dev; struct drm_device *dev = plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(plane); struct intel_plane *intel_plane = to_intel_plane(plane);
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
I915_WRITE(DVSCNTR(pipe), 0); I915_WRITE(DVSCNTR(pipe), 0);
/* Disable the scaler */ /* Disable the scaler */
I915_WRITE(DVSSCALE(pipe), 0); I915_WRITE(DVSSCALE(pipe), 0);
/* Flush double buffered register updates */
I915_WRITE(DVSSURF(pipe), 0); I915_WRITE(DVSSURF(pipe), 0);
POSTING_READ(DVSSURF(pipe));
intel_flush_primary_plane(dev_priv, intel_crtc->plane);
} }
static int static int

8
include/uapi/drm/i915_drm.h
View file

@ -171,8 +171,12 @@ typedef struct _drm_i915_sarea {
#define I915_BOX_TEXTURE_LOAD 0x8 #define I915_BOX_TEXTURE_LOAD 0x8
#define I915_BOX_LOST_CONTEXT 0x10 #define I915_BOX_LOST_CONTEXT 0x10
/* I915 specific ioctls /*
* The device specific ioctl range is 0x40 to 0x79. * i915 specific ioctls.
*
* The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
* [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
* against DRM_COMMAND_BASE and should be between [0x0, 0x60).
*/ */
#define DRM_I915_INIT 0x00 #define DRM_I915_INIT 0x00
#define DRM_I915_FLUSH 0x01 #define DRM_I915_FLUSH 0x01