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documentation: Add alternative release-acquire outcome

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The memory-barriers.txt discussion of local transitivity and
release-acquire chains leaves out discussion of the outcome of
the read from "u".  This commit therefore adds an outcome showing
that you can get a "1" from this read even if the release-acquire
pairs don't line up.

Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
This commit is contained in:
Paul E. McKenney 2016-01-25 22:12:34 -08:00
parent c535cc9292
commit 37ef0341ca
1 changed files with 4 additions and 0 deletions
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4
Documentation/memory-barriers.txt
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@ -1372,6 +1372,10 @@ is possible:
r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0
As an aside, the following outcome is also possible:
r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1
Although cpu0(), cpu1(), and cpu2() will see their respective reads and Although cpu0(), cpu1(), and cpu2() will see their respective reads and
writes in order, CPUs not involved in the release-acquire chain might writes in order, CPUs not involved in the release-acquire chain might
well disagree on the order. This disagreement stems from the fact that well disagree on the order. This disagreement stems from the fact that