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tg3: Move EEE definitions into mdio.h

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In commit 52b02d04c8 entitled "tg3: Add
EEE support", Ben Hutchings had commented that the EEE advertisement
register will be in a standard location.  This patch moves that
definition into mdio.h and changes the code to use it.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson 2010-12-06 08:28:50 +00:00 • committed by David S. Miller
commit 3110f5f554
3 changed files with 13 additions and 11 deletions
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16
drivers/net/tg3.c
View file

@ -32,6 +32,7 @@
#include <linux/etherdevice.h> #include <linux/etherdevice.h>
#include <linux/skbuff.h> #include <linux/skbuff.h>
#include <linux/ethtool.h> #include <linux/ethtool.h>
#include <linux/mdio.h>
#include <linux/mii.h> #include <linux/mii.h>
#include <linux/phy.h> #include <linux/phy.h>
#include <linux/brcmphy.h> #include <linux/brcmphy.h>
@ -1781,7 +1782,8 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
tw32(TG3_CPMU_EEE_CTRL, eeectl); tw32(TG3_CPMU_EEE_CTRL, eeectl);
tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val); tg3_phy_cl45_read(tp, MDIO_MMD_AN,
TG3_CL45_D7_EEERES_STAT, &val);
if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T || if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
val == TG3_CL45_D7_EEERES_STAT_LP_100TX) val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
@ -2987,16 +2989,14 @@ static void tg3_phy_copper_begin(struct tg3 *tp)
if (tp->link_config.autoneg == AUTONEG_ENABLE) { if (tp->link_config.autoneg == AUTONEG_ENABLE) {
/* Advertise 100-BaseTX EEE ability */ /* Advertise 100-BaseTX EEE ability */
if (tp->link_config.advertising & if (tp->link_config.advertising &
(ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full)
ADVERTISED_100baseT_Full)) val |= MDIO_AN_EEE_ADV_100TX;
val |= TG3_CL45_D7_EEEADV_CAP_100TX;
/* Advertise 1000-BaseT EEE ability */ /* Advertise 1000-BaseT EEE ability */
if (tp->link_config.advertising & if (tp->link_config.advertising &
(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)
ADVERTISED_1000baseT_Full)) val |= MDIO_AN_EEE_ADV_1000T;
val |= TG3_CL45_D7_EEEADV_CAP_1000T;
} }
tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val); tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
/* Turn off SM_DSP clock. */ /* Turn off SM_DSP clock. */
val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL | val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |

3
drivers/net/tg3.h
View file

@ -2172,9 +2172,6 @@
#define MII_TG3_TEST1_CRC_EN 0x8000 #define MII_TG3_TEST1_CRC_EN 0x8000
/* Clause 45 expansion registers */ /* Clause 45 expansion registers */
#define TG3_CL45_D7_EEEADV_CAP 0x003c
#define TG3_CL45_D7_EEEADV_CAP_100TX 0x0002
#define TG3_CL45_D7_EEEADV_CAP_1000T 0x0004
#define TG3_CL45_D7_EEERES_STAT 0x803e #define TG3_CL45_D7_EEERES_STAT 0x803e
#define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002 #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
#define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004

5
include/linux/mdio.h
View file

@ -55,6 +55,7 @@
#define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */ #define MDIO_PCS_10GBRT_STAT2 33 /* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */ #define MDIO_AN_10GBT_CTRL 32 /* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */ #define MDIO_AN_10GBT_STAT 33 /* 10GBASE-T auto-negotiation status */
#define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
/* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */ /* LASI (Link Alarm Status Interrupt) registers, defined by XENPAK MSA. */
#define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */ #define MDIO_PMA_LASI_RXCTRL 0x9000 /* RX_ALARM control */
@ -235,6 +236,10 @@
#define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */ #define MDIO_AN_10GBT_STAT_MS 0x4000 /* Master/slave config */
#define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */ #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 /* Master/slave config fault */
/* AN EEE Advertisement register. */
#define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
#define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
/* LASI RX_ALARM control/status registers. */ /* LASI RX_ALARM control/status registers. */
#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */ #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 /* PHY XS RX local fault */
#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */ #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 /* PCS RX local fault */