drm/i915: Remove queue_flip pointer.
With the removal of cs support this is no longer reachable. Can be revived if needed. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1463490484-19540-15-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
This commit is contained in:
Maarten Lankhorst
parent
b8d2afae55
commit
2ee004f7c5
2 changed files with 0 additions and 264 deletions
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@ -618,11 +618,6 @@ struct drm_i915_display_funcs {
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void (*audio_codec_disable)(struct intel_encoder *encoder);
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void (*audio_codec_disable)(struct intel_encoder *encoder);
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void (*fdi_link_train)(struct drm_crtc *crtc);
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void (*fdi_link_train)(struct drm_crtc *crtc);
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void (*init_clock_gating)(struct drm_device *dev);
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void (*init_clock_gating)(struct drm_device *dev);
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int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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struct drm_i915_gem_request *req,
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uint64_t gtt_offset);
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void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
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void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
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/* clock updates for mode set */
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/* clock updates for mode set */
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/* cursor updates */
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/* cursor updates */
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@ -10964,237 +10964,6 @@ void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
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spin_unlock_irqrestore(&dev->event_lock, flags);
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spin_unlock_irqrestore(&dev->event_lock, flags);
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}
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}
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static int intel_gen2_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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struct drm_i915_gem_request *req,
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uint64_t gtt_offset)
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{
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struct intel_engine_cs *engine = req->engine;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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u32 flip_mask;
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int ret;
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ret = intel_ring_begin(req, 6);
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if (ret)
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return ret;
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/* Can't queue multiple flips, so wait for the previous
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* one to finish before executing the next.
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*/
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if (intel_crtc->plane)
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flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
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else
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flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
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intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
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intel_ring_emit(engine, MI_NOOP);
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intel_ring_emit(engine, MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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intel_ring_emit(engine, fb->pitches[0]);
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intel_ring_emit(engine, gtt_offset);
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intel_ring_emit(engine, 0); /* aux display base address, unused */
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return 0;
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}
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static int intel_gen3_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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struct drm_i915_gem_request *req,
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uint64_t gtt_offset)
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{
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struct intel_engine_cs *engine = req->engine;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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u32 flip_mask;
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int ret;
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ret = intel_ring_begin(req, 6);
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if (ret)
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return ret;
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if (intel_crtc->plane)
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flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
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else
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flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
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intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
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intel_ring_emit(engine, MI_NOOP);
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intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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intel_ring_emit(engine, fb->pitches[0]);
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intel_ring_emit(engine, gtt_offset);
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intel_ring_emit(engine, MI_NOOP);
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return 0;
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}
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static int intel_gen4_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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struct drm_i915_gem_request *req,
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uint64_t gtt_offset)
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{
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struct intel_engine_cs *engine = req->engine;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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uint32_t pf, pipesrc;
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int ret;
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ret = intel_ring_begin(req, 4);
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if (ret)
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return ret;
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/* i965+ uses the linear or tiled offsets from the
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* Display Registers (which do not change across a page-flip)
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* so we need only reprogram the base address.
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*/
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intel_ring_emit(engine, MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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intel_ring_emit(engine, fb->pitches[0]);
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intel_ring_emit(engine, gtt_offset | obj->tiling_mode);
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/* XXX Enabling the panel-fitter across page-flip is so far
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* untested on non-native modes, so ignore it for now.
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* pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
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*/
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pf = 0;
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pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
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intel_ring_emit(engine, pf | pipesrc);
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return 0;
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}
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static int intel_gen6_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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struct drm_i915_gem_request *req,
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uint64_t gtt_offset)
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{
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struct intel_engine_cs *engine = req->engine;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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uint32_t pf, pipesrc;
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int ret;
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ret = intel_ring_begin(req, 4);
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if (ret)
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return ret;
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intel_ring_emit(engine, MI_DISPLAY_FLIP |
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MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
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intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
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intel_ring_emit(engine, gtt_offset);
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/* Contrary to the suggestions in the documentation,
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* "Enable Panel Fitter" does not seem to be required when page
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* flipping with a non-native mode, and worse causes a normal
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* modeset to fail.
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* pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
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*/
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pf = 0;
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pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
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intel_ring_emit(engine, pf | pipesrc);
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return 0;
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}
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static int intel_gen7_queue_flip(struct drm_device *dev,
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struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_i915_gem_object *obj,
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struct drm_i915_gem_request *req,
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uint64_t gtt_offset)
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{
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struct intel_engine_cs *engine = req->engine;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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uint32_t plane_bit = 0;
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int len, ret;
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switch (intel_crtc->plane) {
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case PLANE_A:
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plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
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break;
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case PLANE_B:
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plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
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break;
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case PLANE_C:
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plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
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break;
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default:
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WARN_ONCE(1, "unknown plane in flip command\n");
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return -ENODEV;
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}
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len = 4;
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if (engine->id == RCS) {
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len += 6;
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/*
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* On Gen 8, SRM is now taking an extra dword to accommodate
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* 48bits addresses, and we need a NOOP for the batch size to
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* stay even.
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*/
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if (IS_GEN8(dev))
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len += 2;
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}
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/*
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* BSpec MI_DISPLAY_FLIP for IVB:
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* "The full packet must be contained within the same cache line."
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*
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* Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
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* cacheline, if we ever start emitting more commands before
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* the MI_DISPLAY_FLIP we may need to first emit everything else,
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* then do the cacheline alignment, and finally emit the
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* MI_DISPLAY_FLIP.
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*/
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ret = intel_ring_cacheline_align(req);
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if (ret)
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return ret;
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ret = intel_ring_begin(req, len);
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if (ret)
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return ret;
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/* Unmask the flip-done completion message. Note that the bspec says that
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* we should do this for both the BCS and RCS, and that we must not unmask
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* more than one flip event at any time (or ensure that one flip message
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* can be sent by waiting for flip-done prior to queueing new flips).
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* Experimentation says that BCS works despite DERRMR masking all
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* flip-done completion events and that unmasking all planes at once
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* for the RCS also doesn't appear to drop events. Setting the DERRMR
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* to zero does lead to lockups within MI_DISPLAY_FLIP.
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*/
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if (engine->id == RCS) {
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intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
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intel_ring_emit_reg(engine, DERRMR);
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intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
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DERRMR_PIPEB_PRI_FLIP_DONE |
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DERRMR_PIPEC_PRI_FLIP_DONE));
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if (IS_GEN8(dev))
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intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
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MI_SRM_LRM_GLOBAL_GTT);
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else
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intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
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MI_SRM_LRM_GLOBAL_GTT);
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intel_ring_emit_reg(engine, DERRMR);
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intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
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if (IS_GEN8(dev)) {
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intel_ring_emit(engine, 0);
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intel_ring_emit(engine, MI_NOOP);
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}
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}
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intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
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intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
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intel_ring_emit(engine, gtt_offset);
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intel_ring_emit(engine, (MI_NOOP));
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return 0;
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}
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static void intel_mmio_flip_work_func(struct work_struct *w)
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static void intel_mmio_flip_work_func(struct work_struct *w)
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{
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{
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struct intel_flip_work *work =
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struct intel_flip_work *work =
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@ -14752,34 +14521,6 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
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dev_priv->display.modeset_calc_cdclk =
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dev_priv->display.modeset_calc_cdclk =
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broxton_modeset_calc_cdclk;
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broxton_modeset_calc_cdclk;
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}
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}
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switch (INTEL_INFO(dev_priv)->gen) {
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case 2:
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dev_priv->display.queue_flip = intel_gen2_queue_flip;
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break;
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case 3:
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dev_priv->display.queue_flip = intel_gen3_queue_flip;
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break;
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case 4:
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case 5:
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dev_priv->display.queue_flip = intel_gen4_queue_flip;
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break;
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case 6:
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dev_priv->display.queue_flip = intel_gen6_queue_flip;
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break;
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case 7:
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case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
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dev_priv->display.queue_flip = intel_gen7_queue_flip;
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break;
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case 9:
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/* Drop through - unsupported since execlist only. */
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default:
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/* Default just returns -ENODEV to indicate unsupported */
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break;
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}
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}
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}
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/*
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/*
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