Immutable branch between MFD and Extcon due for v3.16 merge-window.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTV7vmAAoJEFGvii+H/HdhStcQAIPXONkcTtnRijYYVo4+zMfY 5lyEc7bpboK3FJW0SrSM3gt6jSjFayz7HN+oVd5ez73XYlKr+X4oap6GD1VnP+r2 d2kc0ccfRa5oMPdeth0xabwmXnG2Cm3i3EwLGZAjxRAI72nmmTJu08HSWYSw9tBs oxKLuuYNhdIRAoEHrA5wyymb4fq2AdQrdNGEXZ9utZEK7z0+DRxD3LxeNEiW8dU2 pU9XXlEbp9gQKsyiRL+MPxuFH7C7QpaQN1aryKupHEHtuRPjxqIsXETUsmxGt+sQ P3jN3FayYRYknqWSda+/lgEjkzw0CgeLFpR13emt5P2K8K8NPcV17mHhggWxFaes iGPi9cgotV9X2zxAgayAusunPRHEQ8Yz7bnQsXBuH04CbBgnu53gBUQyELQhJ2xO HBG6VVn5kXCpb80OWX/lTefEIN3yfuH15eV/cmBk3Qu6qqVFjCg6cBqi2b5QFPYN 8ks/58ewbhKqh+T+yr7N70sXIfOF9aBIqREdnlp/uXaCYLkylSNaUPpxZTllDUnE QoJVTMwb/BgGKolhpfwva2UkVPt5C50w1+mNLh05d9IMF/C9kyQMcsC7rOa229LU XwtDoWFUTMzjNqTRBTLdElfkEnEET07xDvv3SQTAj30eTCaQs0+gxDMNSrDN/0zN u6uUTp1grfVVOoz1FPcS =q4Ul -----END PGP SIGNATURE----- mergetag objecta613b739b8type commit tag ib-mfd-omap-3.16 tagger Lee Jones <lee.jones@linaro.org> 1398263769 +0100 Immutable branch between MFD and ARM OMAP due for v3.16 merge-window. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTV9ADAAoJEFGvii+H/HdhPhkP/1Xoc6APceeJaX8jOmx0rxzQ PhYl3er5b3eYtxgGR8s8FrdVrYNyEytGZtMoQN3EYhVnq/ZvbPkR8zMruDszUHYP PBfcZJi4GBJIAQU30a8Dvla8UtFaph+IoxSd6E4hSIvb+UFjSvi9ZjQYX82gFop4 TLeAPW4byQP2YKSkDUq5WzzMLbjQ+ZanJSrueYXmu4VOVgtA0+nBWVj5B8PD1m+O 2Sp2vhdCPCgIsChQZl3i9h2HroUtomnNWeCdv0YzOwISlvUv+aBg7khK35Jtw7v3 YeAx3YelQ3z2dnFS/ddEvLKthuTV5BfyGq+dJjMwBLrOv81rzHFBYLCRiABB0RgD EUEAv3IJ31SpjrsO0uXnGFp69gMsJgOwLRcjM8TfUi+Wd4YQcbl/tCYX2k7voJ6u fbpqarr1zgZpV7r1cX2ivsm8VY2bzQ7p2Dh681oQtHyM+RC94dVvGS0cAaVlnhYY MtJWEdtpY3hRcx5qVE8+8wf5RYyXjluhme1EGhO8VL13hMw7ofmtfl2OKN4WAsYO KIDMTVJ9RneUQQ6FOx270x17Gp01vxoHIV6pBMi7Uo65l7xrs2YEfgUJhp4eCVXT dD4appF5q090UwD7lYADztQZ8RB5GLELZH6Vkpw3qPtfqM97zSy9IFMzTxn446ic vdktkG6GJab2vg3mLxDf =izRQ -----END PGP SIGNATURE----- mergetag objectc42ba72ec3type commit tag ib-mfd-regulator-3.16 tagger Lee Jones <lee.jones@linaro.org> 1398675220 +0100 Immutable branch between MFD and Regulator due for v3.16 merge-window. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTXhcuAAoJEFGvii+H/HdhoJEQAI15rEldcSpzLCYiinEfiKUI d+6zn5Gx6pKtkfCWdplHxM82Fe5H/kbgCLq+SSCQ6DFrOGXC34i4JnmhdCvcaU/K OEtXsG1i2PNzJwMFcnXVW5wD6LnS/b+243XtBtfQ887j9A1R2tEM9ka+i5AP3+O2 NoBT9DshWWnj16CRJbMMFgNqDI6+QUoirgKzOXLp9stuzrThYU7kaluyMmMUREAx tXl8jOBH2Nu0YBiVi6Cgn1xNqtX0Snc9UU1QcugJzuPtyseFsQGUp1cP/ahmeP0y EFzKoDbKpag1BV/IEsKWfiD6KEEPFd3IUcZugXIhlRKSGsEcIRTeu6PBFMq9FssF hfajzbTw7aDFmYq3Ifc4V6MGtalnCoJz0bsM5XA1voWqXJ+9Tqp4p/5xbJVn2ObA /e8k5ljeRH+PBuRKrxgmJJUP3n/QXlJMZ+IrI3BTSeMLu2xZ1U95ynbHO8s3Dxdd CpX4xbDq82cBn+JNG3K9+l8XTZUdaWwEQ18VylVcbBdEa4jS2lMyYKIFCJiERLNt LCD6hzMGjF7/qVeXhi9AyITEe1XrFSjeTv8WH2R3C4vVXLcjQ3bCnWTFlszbGBsK /H0dUWg0HofMrR/oATydWtrgj5F+1aEIdZZqDU0hUCvC849c62zprqXUe7TbP6FT yvAlikr5PGMIWw89DCn1 =NGmT -----END PGP SIGNATURE----- Merge branches 'ib-from-asoc-3.16', 'ib-from-pm-3.16', 'ib-from-regulator-3.16', 'ib-mfd-gpio-3.16' and 'ib-mfd-mmc-memstick-3.16', tags 'ib-mfd-extcon-3.16', 'ib-mfd-omap-3.16' and 'ib-mfd-regulator-3.16' into ibs-for-mfd-merged
This commit is contained in:
Lee Jones
parent
4b660a7f5c
780aaeff96
fdb56c45a2
4bd5e3049b
8a82b408ac
9e9dc7d959
99451dceeb
a613b739b8
c42ba72ec3
commit
28fee3fa0e
54 changed files with 3670 additions and 500 deletions
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@ -124,4 +124,7 @@ int wm5102_patch(struct arizona *arizona);
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int wm5110_patch(struct arizona *arizona);
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int wm8997_patch(struct arizona *arizona);
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extern int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop,
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bool mandatory);
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#endif
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@ -1,7 +1,7 @@
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/*
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* max14577-private.h - Common API for the Maxim 14577 internal sub chip
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* max14577-private.h - Common API for the Maxim 14577/77836 internal sub chip
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*
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* Copyright (C) 2013 Samsung Electrnoics
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* Copyright (C) 2014 Samsung Electrnoics
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* Chanwoo Choi <cw00.choi@samsung.com>
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* Krzysztof Kozlowski <k.kozlowski@samsung.com>
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*
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@ -22,9 +22,19 @@
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#define MAX14577_REG_INVALID (0xff)
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#define I2C_ADDR_PMIC (0x46 >> 1)
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#define I2C_ADDR_MUIC (0x4A >> 1)
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#define I2C_ADDR_FG (0x6C >> 1)
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/* Slave addr = 0x4A: Interrupt */
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enum maxim_device_type {
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MAXIM_DEVICE_TYPE_UNKNOWN = 0,
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MAXIM_DEVICE_TYPE_MAX14577,
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MAXIM_DEVICE_TYPE_MAX77836,
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MAXIM_DEVICE_TYPE_NUM,
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};
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/* Slave addr = 0x4A: MUIC and Charger */
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enum max14577_reg {
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MAX14577_REG_DEVICEID = 0x00,
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MAX14577_REG_INT1 = 0x01,
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@ -74,20 +84,22 @@ enum max14577_muic_charger_type {
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};
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/* MAX14577 interrupts */
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#define INT1_ADC_MASK (0x1 << 0)
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#define INT1_ADCLOW_MASK (0x1 << 1)
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#define INT1_ADCERR_MASK (0x1 << 2)
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#define MAX14577_INT1_ADC_MASK BIT(0)
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#define MAX14577_INT1_ADCLOW_MASK BIT(1)
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#define MAX14577_INT1_ADCERR_MASK BIT(2)
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#define MAX77836_INT1_ADC1K_MASK BIT(3)
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#define INT2_CHGTYP_MASK (0x1 << 0)
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#define INT2_CHGDETRUN_MASK (0x1 << 1)
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#define INT2_DCDTMR_MASK (0x1 << 2)
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#define INT2_DBCHG_MASK (0x1 << 3)
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#define INT2_VBVOLT_MASK (0x1 << 4)
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#define MAX14577_INT2_CHGTYP_MASK BIT(0)
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#define MAX14577_INT2_CHGDETRUN_MASK BIT(1)
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#define MAX14577_INT2_DCDTMR_MASK BIT(2)
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#define MAX14577_INT2_DBCHG_MASK BIT(3)
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#define MAX14577_INT2_VBVOLT_MASK BIT(4)
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#define MAX77836_INT2_VIDRM_MASK BIT(5)
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#define INT3_EOC_MASK (0x1 << 0)
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#define INT3_CGMBC_MASK (0x1 << 1)
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#define INT3_OVP_MASK (0x1 << 2)
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#define INT3_MBCCHGERR_MASK (0x1 << 3)
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#define MAX14577_INT3_EOC_MASK BIT(0)
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#define MAX14577_INT3_CGMBC_MASK BIT(1)
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#define MAX14577_INT3_OVP_MASK BIT(2)
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#define MAX14577_INT3_MBCCHGERR_MASK BIT(3)
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/* MAX14577 DEVICE ID register */
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#define DEVID_VENDORID_SHIFT 0
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@ -99,9 +111,11 @@ enum max14577_muic_charger_type {
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#define STATUS1_ADC_SHIFT 0
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#define STATUS1_ADCLOW_SHIFT 5
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#define STATUS1_ADCERR_SHIFT 6
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#define MAX77836_STATUS1_ADC1K_SHIFT 7
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#define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
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#define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
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#define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
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#define STATUS1_ADCLOW_MASK BIT(STATUS1_ADCLOW_SHIFT)
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#define STATUS1_ADCERR_MASK BIT(STATUS1_ADCERR_SHIFT)
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#define MAX77836_STATUS1_ADC1K_MASK BIT(MAX77836_STATUS1_ADC1K_SHIFT)
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/* MAX14577 STATUS2 register */
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#define STATUS2_CHGTYP_SHIFT 0
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@ -109,11 +123,13 @@ enum max14577_muic_charger_type {
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#define STATUS2_DCDTMR_SHIFT 4
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#define STATUS2_DBCHG_SHIFT 5
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#define STATUS2_VBVOLT_SHIFT 6
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#define MAX77836_STATUS2_VIDRM_SHIFT 7
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#define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
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#define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
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#define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
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#define STATUS2_DBCHG_MASK (0x1 << STATUS2_DBCHG_SHIFT)
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#define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
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#define STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT)
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#define STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT)
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#define STATUS2_DBCHG_MASK BIT(STATUS2_DBCHG_SHIFT)
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#define STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT)
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#define MAX77836_STATUS2_VIDRM_MASK BIT(MAX77836_STATUS2_VIDRM_SHIFT)
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/* MAX14577 CONTROL1 register */
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#define COMN1SW_SHIFT 0
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@ -122,8 +138,8 @@ enum max14577_muic_charger_type {
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#define IDBEN_SHIFT 7
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#define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
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#define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
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#define MICEN_MASK (0x1 << MICEN_SHIFT)
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#define IDBEN_MASK (0x1 << IDBEN_SHIFT)
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#define MICEN_MASK BIT(MICEN_SHIFT)
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#define IDBEN_MASK BIT(IDBEN_SHIFT)
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#define CLEAR_IDBEN_MICEN_MASK (COMN1SW_MASK | COMP2SW_MASK)
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#define CTRL1_SW_USB ((1 << COMP2SW_SHIFT) \
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| (1 << COMN1SW_SHIFT))
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@ -143,14 +159,14 @@ enum max14577_muic_charger_type {
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#define CTRL2_ACCDET_SHIFT (5)
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#define CTRL2_USBCPINT_SHIFT (6)
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#define CTRL2_RCPS_SHIFT (7)
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#define CTRL2_LOWPWR_MASK (0x1 << CTRL2_LOWPWR_SHIFT)
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#define CTRL2_ADCEN_MASK (0x1 << CTRL2_ADCEN_SHIFT)
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#define CTRL2_CPEN_MASK (0x1 << CTRL2_CPEN_SHIFT)
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#define CTRL2_SFOUTASRT_MASK (0x1 << CTRL2_SFOUTASRT_SHIFT)
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#define CTRL2_SFOUTORD_MASK (0x1 << CTRL2_SFOUTORD_SHIFT)
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#define CTRL2_ACCDET_MASK (0x1 << CTRL2_ACCDET_SHIFT)
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#define CTRL2_USBCPINT_MASK (0x1 << CTRL2_USBCPINT_SHIFT)
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#define CTRL2_RCPS_MASK (0x1 << CTR2_RCPS_SHIFT)
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#define CTRL2_LOWPWR_MASK BIT(CTRL2_LOWPWR_SHIFT)
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#define CTRL2_ADCEN_MASK BIT(CTRL2_ADCEN_SHIFT)
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#define CTRL2_CPEN_MASK BIT(CTRL2_CPEN_SHIFT)
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#define CTRL2_SFOUTASRT_MASK BIT(CTRL2_SFOUTASRT_SHIFT)
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#define CTRL2_SFOUTORD_MASK BIT(CTRL2_SFOUTORD_SHIFT)
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#define CTRL2_ACCDET_MASK BIT(CTRL2_ACCDET_SHIFT)
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#define CTRL2_USBCPINT_MASK BIT(CTRL2_USBCPINT_SHIFT)
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#define CTRL2_RCPS_MASK BIT(CTRL2_RCPS_SHIFT)
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#define CTRL2_CPEN1_LOWPWR0 ((1 << CTRL2_CPEN_SHIFT) | \
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(0 << CTRL2_LOWPWR_SHIFT))
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@ -198,14 +214,14 @@ enum max14577_charger_reg {
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#define CDETCTRL1_DBEXIT_SHIFT 5
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#define CDETCTRL1_DBIDLE_SHIFT 6
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#define CDETCTRL1_CDPDET_SHIFT 7
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#define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
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#define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
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#define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
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#define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
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#define CDETCTRL1_DCHKTM_MASK (0x1 << CDETCTRL1_DCHKTM_SHIFT)
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#define CDETCTRL1_DBEXIT_MASK (0x1 << CDETCTRL1_DBEXIT_SHIFT)
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#define CDETCTRL1_DBIDLE_MASK (0x1 << CDETCTRL1_DBIDLE_SHIFT)
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#define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
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#define CDETCTRL1_CHGDETEN_MASK BIT(CDETCTRL1_CHGDETEN_SHIFT)
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#define CDETCTRL1_CHGTYPMAN_MASK BIT(CDETCTRL1_CHGTYPMAN_SHIFT)
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#define CDETCTRL1_DCDEN_MASK BIT(CDETCTRL1_DCDEN_SHIFT)
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#define CDETCTRL1_DCD2SCT_MASK BIT(CDETCTRL1_DCD2SCT_SHIFT)
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#define CDETCTRL1_DCHKTM_MASK BIT(CDETCTRL1_DCHKTM_SHIFT)
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#define CDETCTRL1_DBEXIT_MASK BIT(CDETCTRL1_DBEXIT_SHIFT)
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#define CDETCTRL1_DBIDLE_MASK BIT(CDETCTRL1_DBIDLE_SHIFT)
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#define CDETCTRL1_CDPDET_MASK BIT(CDETCTRL1_CDPDET_SHIFT)
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/* MAX14577 CHGCTRL1 register */
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#define CHGCTRL1_TCHW_SHIFT 4
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/* MAX14577 CHGCTRL2 register */
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#define CHGCTRL2_MBCHOSTEN_SHIFT 6
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#define CHGCTRL2_MBCHOSTEN_MASK (0x1 << CHGCTRL2_MBCHOSTEN_SHIFT)
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#define CHGCTRL2_MBCHOSTEN_MASK BIT(CHGCTRL2_MBCHOSTEN_SHIFT)
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#define CHGCTRL2_VCHGR_RC_SHIFT 7
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#define CHGCTRL2_VCHGR_RC_MASK (0x1 << CHGCTRL2_VCHGR_RC_SHIFT)
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#define CHGCTRL2_VCHGR_RC_MASK BIT(CHGCTRL2_VCHGR_RC_SHIFT)
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/* MAX14577 CHGCTRL3 register */
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#define CHGCTRL3_MBCCVWRC_SHIFT 0
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#define CHGCTRL4_MBCICHWRCH_SHIFT 0
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#define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
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#define CHGCTRL4_MBCICHWRCL_SHIFT 4
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#define CHGCTRL4_MBCICHWRCL_MASK (0x1 << CHGCTRL4_MBCICHWRCL_SHIFT)
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#define CHGCTRL4_MBCICHWRCL_MASK BIT(CHGCTRL4_MBCICHWRCL_SHIFT)
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/* MAX14577 CHGCTRL5 register */
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#define CHGCTRL5_EOCS_SHIFT 0
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/* MAX14577 CHGCTRL6 register */
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#define CHGCTRL6_AUTOSTOP_SHIFT 5
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#define CHGCTRL6_AUTOSTOP_MASK (0x1 << CHGCTRL6_AUTOSTOP_SHIFT)
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#define CHGCTRL6_AUTOSTOP_MASK BIT(CHGCTRL6_AUTOSTOP_SHIFT)
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/* MAX14577 CHGCTRL7 register */
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#define CHGCTRL7_OTPCGHCVS_SHIFT 0
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@ -245,14 +261,111 @@ enum max14577_charger_reg {
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#define MAX14577_REGULATOR_CURRENT_LIMIT_HIGH_STEP 50000
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#define MAX14577_REGULATOR_CURRENT_LIMIT_MAX 950000
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/* MAX77836 regulator current limits (as in CHGCTRL4 register), uA */
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#define MAX77836_REGULATOR_CURRENT_LIMIT_MIN 45000
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#define MAX77836_REGULATOR_CURRENT_LIMIT_HIGH_START 100000
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#define MAX77836_REGULATOR_CURRENT_LIMIT_HIGH_STEP 25000
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#define MAX77836_REGULATOR_CURRENT_LIMIT_MAX 475000
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/* MAX14577 regulator SFOUT LDO voltage, fixed, uV */
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#define MAX14577_REGULATOR_SAFEOUT_VOLTAGE 4900000
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/* MAX77836 regulator LDOx voltage, uV */
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#define MAX77836_REGULATOR_LDO_VOLTAGE_MIN 800000
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#define MAX77836_REGULATOR_LDO_VOLTAGE_MAX 3950000
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#define MAX77836_REGULATOR_LDO_VOLTAGE_STEP 50000
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#define MAX77836_REGULATOR_LDO_VOLTAGE_STEPS_NUM 64
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/* Slave addr = 0x46: PMIC */
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enum max77836_pmic_reg {
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MAX77836_PMIC_REG_PMIC_ID = 0x20,
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MAX77836_PMIC_REG_PMIC_REV = 0x21,
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MAX77836_PMIC_REG_INTSRC = 0x22,
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MAX77836_PMIC_REG_INTSRC_MASK = 0x23,
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MAX77836_PMIC_REG_TOPSYS_INT = 0x24,
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MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26,
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MAX77836_PMIC_REG_TOPSYS_STAT = 0x28,
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MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A,
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MAX77836_PMIC_REG_LSCNFG = 0x2B,
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MAX77836_LDO_REG_CNFG1_LDO1 = 0x51,
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MAX77836_LDO_REG_CNFG2_LDO1 = 0x52,
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MAX77836_LDO_REG_CNFG1_LDO2 = 0x53,
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MAX77836_LDO_REG_CNFG2_LDO2 = 0x54,
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MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55,
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MAX77836_COMP_REG_COMP1 = 0x60,
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MAX77836_PMIC_REG_END,
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};
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#define MAX77836_INTSRC_MASK_TOP_INT_SHIFT 1
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#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT 3
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#define MAX77836_INTSRC_MASK_TOP_INT_MASK BIT(MAX77836_INTSRC_MASK_TOP_INT_SHIFT)
|
||||
#define MAX77836_INTSRC_MASK_MUIC_CHG_INT_MASK BIT(MAX77836_INTSRC_MASK_MUIC_CHG_INT_SHIFT)
|
||||
|
||||
/* MAX77836 PMIC interrupts */
|
||||
#define MAX77836_TOPSYS_INT_T120C_SHIFT 0
|
||||
#define MAX77836_TOPSYS_INT_T140C_SHIFT 1
|
||||
#define MAX77836_TOPSYS_INT_T120C_MASK BIT(MAX77836_TOPSYS_INT_T120C_SHIFT)
|
||||
#define MAX77836_TOPSYS_INT_T140C_MASK BIT(MAX77836_TOPSYS_INT_T140C_SHIFT)
|
||||
|
||||
/* LDO1/LDO2 CONFIG1 register */
|
||||
#define MAX77836_CNFG1_LDO_PWRMD_SHIFT 6
|
||||
#define MAX77836_CNFG1_LDO_TV_SHIFT 0
|
||||
#define MAX77836_CNFG1_LDO_PWRMD_MASK (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT)
|
||||
#define MAX77836_CNFG1_LDO_TV_MASK (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT)
|
||||
|
||||
/* LDO1/LDO2 CONFIG2 register */
|
||||
#define MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT 7
|
||||
#define MAX77836_CNFG2_LDO_ALPMEN_SHIFT 6
|
||||
#define MAX77836_CNFG2_LDO_COMP_SHIFT 4
|
||||
#define MAX77836_CNFG2_LDO_POK_SHIFT 3
|
||||
#define MAX77836_CNFG2_LDO_ADE_SHIFT 1
|
||||
#define MAX77836_CNFG2_LDO_SS_SHIFT 0
|
||||
#define MAX77836_CNFG2_LDO_OVCLMPEN_MASK BIT(MAX77836_CNFG2_LDO_OVCLMPEN_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_ALPMEN_MASK BIT(MAX77836_CNFG2_LDO_ALPMEN_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_COMP_MASK (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_POK_MASK BIT(MAX77836_CNFG2_LDO_POK_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_ADE_MASK BIT(MAX77836_CNFG2_LDO_ADE_SHIFT)
|
||||
#define MAX77836_CNFG2_LDO_SS_MASK BIT(MAX77836_CNFG2_LDO_SS_SHIFT)
|
||||
|
||||
/* Slave addr = 0x6C: Fuel-Gauge/Battery */
|
||||
enum max77836_fg_reg {
|
||||
MAX77836_FG_REG_VCELL_MSB = 0x02,
|
||||
MAX77836_FG_REG_VCELL_LSB = 0x03,
|
||||
MAX77836_FG_REG_SOC_MSB = 0x04,
|
||||
MAX77836_FG_REG_SOC_LSB = 0x05,
|
||||
MAX77836_FG_REG_MODE_H = 0x06,
|
||||
MAX77836_FG_REG_MODE_L = 0x07,
|
||||
MAX77836_FG_REG_VERSION_MSB = 0x08,
|
||||
MAX77836_FG_REG_VERSION_LSB = 0x09,
|
||||
MAX77836_FG_REG_HIBRT_H = 0x0A,
|
||||
MAX77836_FG_REG_HIBRT_L = 0x0B,
|
||||
MAX77836_FG_REG_CONFIG_H = 0x0C,
|
||||
MAX77836_FG_REG_CONFIG_L = 0x0D,
|
||||
MAX77836_FG_REG_VALRT_MIN = 0x14,
|
||||
MAX77836_FG_REG_VALRT_MAX = 0x15,
|
||||
MAX77836_FG_REG_CRATE_MSB = 0x16,
|
||||
MAX77836_FG_REG_CRATE_LSB = 0x17,
|
||||
MAX77836_FG_REG_VRESET = 0x18,
|
||||
MAX77836_FG_REG_FGID = 0x19,
|
||||
MAX77836_FG_REG_STATUS_H = 0x1A,
|
||||
MAX77836_FG_REG_STATUS_L = 0x1B,
|
||||
/*
|
||||
* TODO: TABLE registers
|
||||
* TODO: CMD register
|
||||
*/
|
||||
|
||||
MAX77836_FG_REG_END,
|
||||
};
|
||||
|
||||
enum max14577_irq {
|
||||
/* INT1 */
|
||||
MAX14577_IRQ_INT1_ADC,
|
||||
MAX14577_IRQ_INT1_ADCLOW,
|
||||
MAX14577_IRQ_INT1_ADCERR,
|
||||
MAX77836_IRQ_INT1_ADC1K,
|
||||
|
||||
/* INT2 */
|
||||
MAX14577_IRQ_INT2_CHGTYP,
|
||||
|
|
@ -260,6 +373,7 @@ enum max14577_irq {
|
|||
MAX14577_IRQ_INT2_DCDTMR,
|
||||
MAX14577_IRQ_INT2_DBCHG,
|
||||
MAX14577_IRQ_INT2_VBVOLT,
|
||||
MAX77836_IRQ_INT2_VIDRM,
|
||||
|
||||
/* INT3 */
|
||||
MAX14577_IRQ_INT3_EOC,
|
||||
|
|
@ -267,21 +381,25 @@ enum max14577_irq {
|
|||
MAX14577_IRQ_INT3_OVP,
|
||||
MAX14577_IRQ_INT3_MBCCHGERR,
|
||||
|
||||
/* TOPSYS_INT, only MAX77836 */
|
||||
MAX77836_IRQ_TOPSYS_T140C,
|
||||
MAX77836_IRQ_TOPSYS_T120C,
|
||||
|
||||
MAX14577_IRQ_NUM,
|
||||
};
|
||||
|
||||
struct max14577 {
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c; /* Slave addr = 0x4A */
|
||||
struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */
|
||||
enum maxim_device_type dev_type;
|
||||
|
||||
struct regmap *regmap;
|
||||
struct regmap *regmap; /* For MUIC and Charger */
|
||||
struct regmap *regmap_pmic;
|
||||
|
||||
struct regmap_irq_chip_data *irq_data;
|
||||
struct regmap_irq_chip_data *irq_data; /* For MUIC and Charger */
|
||||
struct regmap_irq_chip_data *irq_data_pmic;
|
||||
int irq;
|
||||
|
||||
/* Device ID */
|
||||
u8 vendor_id; /* Vendor Identification */
|
||||
u8 device_id; /* Chip Version */
|
||||
};
|
||||
|
||||
/* MAX14577 shared regmap API function */
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* max14577.h - Driver for the Maxim 14577
|
||||
* max14577.h - Driver for the Maxim 14577/77836
|
||||
*
|
||||
* Copyright (C) 2013 Samsung Electrnoics
|
||||
* Copyright (C) 2014 Samsung Electrnoics
|
||||
* Chanwoo Choi <cw00.choi@samsung.com>
|
||||
* Krzysztof Kozlowski <k.kozlowski@samsung.com>
|
||||
*
|
||||
|
|
@ -20,6 +20,9 @@
|
|||
* MAX14577 has MUIC, Charger devices.
|
||||
* The devices share the same I2C bus and interrupt line
|
||||
* included in this mfd driver.
|
||||
*
|
||||
* MAX77836 has additional PMIC and Fuel-Gauge on different I2C slave
|
||||
* addresses.
|
||||
*/
|
||||
|
||||
#ifndef __MAX14577_H__
|
||||
|
|
@ -32,7 +35,17 @@ enum max14577_regulators {
|
|||
MAX14577_SAFEOUT = 0,
|
||||
MAX14577_CHARGER,
|
||||
|
||||
MAX14577_REG_MAX,
|
||||
MAX14577_REGULATOR_NUM,
|
||||
};
|
||||
|
||||
/* MAX77836 regulator IDs */
|
||||
enum max77836_regulators {
|
||||
MAX77836_SAFEOUT = 0,
|
||||
MAX77836_CHARGER,
|
||||
MAX77836_LDO1,
|
||||
MAX77836_LDO2,
|
||||
|
||||
MAX77836_REGULATOR_NUM,
|
||||
};
|
||||
|
||||
struct max14577_regulator_platform_data {
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
#include <linux/mutex.h>
|
||||
|
||||
struct device;
|
||||
struct regulator;
|
||||
|
||||
enum stmpe_block {
|
||||
STMPE_BLOCK_GPIO = 1 << 0,
|
||||
|
|
@ -62,6 +63,8 @@ struct stmpe_client_info;
|
|||
|
||||
/**
|
||||
* struct stmpe - STMPE MFD structure
|
||||
* @vcc: optional VCC regulator
|
||||
* @vio: optional VIO regulator
|
||||
* @lock: lock protecting I/O operations
|
||||
* @irq_lock: IRQ bus lock
|
||||
* @dev: device, mostly for dev_dbg()
|
||||
|
|
@ -73,13 +76,14 @@ struct stmpe_client_info;
|
|||
* @regs: list of addresses of registers which are at different addresses on
|
||||
* different variants. Indexed by one of STMPE_IDX_*.
|
||||
* @irq: irq number for stmpe
|
||||
* @irq_base: starting IRQ number for internal IRQs
|
||||
* @num_gpios: number of gpios, differs for variants
|
||||
* @ier: cache of IER registers for bus_lock
|
||||
* @oldier: cache of IER registers for bus_lock
|
||||
* @pdata: platform data
|
||||
*/
|
||||
struct stmpe {
|
||||
struct regulator *vcc;
|
||||
struct regulator *vio;
|
||||
struct mutex lock;
|
||||
struct mutex irq_lock;
|
||||
struct device *dev;
|
||||
|
|
@ -91,7 +95,6 @@ struct stmpe {
|
|||
const u8 *regs;
|
||||
|
||||
int irq;
|
||||
int irq_base;
|
||||
int num_gpios;
|
||||
u8 ier[2];
|
||||
u8 oldier[2];
|
||||
|
|
@ -132,8 +135,6 @@ struct stmpe_keypad_platform_data {
|
|||
|
||||
/**
|
||||
* struct stmpe_gpio_platform_data - STMPE GPIO platform data
|
||||
* @gpio_base: first gpio number assigned. A maximum of
|
||||
* %STMPE_NR_GPIOS GPIOs will be allocated.
|
||||
* @norequest_mask: bitmask specifying which GPIOs should _not_ be
|
||||
* requestable due to different usage (e.g. touch, keypad)
|
||||
* STMPE_GPIO_NOREQ_* macros can be used here.
|
||||
|
|
@ -141,7 +142,6 @@ struct stmpe_keypad_platform_data {
|
|||
* @remove: board specific remove callback
|
||||
*/
|
||||
struct stmpe_gpio_platform_data {
|
||||
int gpio_base;
|
||||
unsigned norequest_mask;
|
||||
void (*setup)(struct stmpe *stmpe, unsigned gpio_base);
|
||||
void (*remove)(struct stmpe *stmpe, unsigned gpio_base);
|
||||
|
|
@ -195,8 +195,6 @@ struct stmpe_ts_platform_data {
|
|||
* @irq_trigger: IRQ trigger to use for the interrupt to the host
|
||||
* @autosleep: bool to enable/disable stmpe autosleep
|
||||
* @autosleep_timeout: inactivity timeout in milliseconds for autosleep
|
||||
* @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
|
||||
* %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
|
||||
* @irq_over_gpio: true if gpio is used to get irq
|
||||
* @irq_gpio: gpio number over which irq will be requested (significant only if
|
||||
* irq_over_gpio is true)
|
||||
|
|
@ -207,7 +205,6 @@ struct stmpe_ts_platform_data {
|
|||
struct stmpe_platform_data {
|
||||
int id;
|
||||
unsigned int blocks;
|
||||
int irq_base;
|
||||
unsigned int irq_trigger;
|
||||
bool autosleep;
|
||||
bool irq_over_gpio;
|
||||
|
|
@ -219,10 +216,4 @@ struct stmpe_platform_data {
|
|||
struct stmpe_ts_platform_data *ts;
|
||||
};
|
||||
|
||||
#define STMPE_NR_INTERNAL_IRQS 9
|
||||
#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
|
||||
|
||||
#define STMPE_NR_GPIOS 24
|
||||
#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -64,6 +64,20 @@ enum {
|
|||
TPS65090_REGULATOR_MAX,
|
||||
};
|
||||
|
||||
/* Register addresses */
|
||||
#define TPS65090_REG_INTR_STS 0x00
|
||||
#define TPS65090_REG_INTR_STS2 0x01
|
||||
#define TPS65090_REG_INTR_MASK 0x02
|
||||
#define TPS65090_REG_INTR_MASK2 0x03
|
||||
#define TPS65090_REG_CG_CTRL0 0x04
|
||||
#define TPS65090_REG_CG_CTRL1 0x05
|
||||
#define TPS65090_REG_CG_CTRL2 0x06
|
||||
#define TPS65090_REG_CG_CTRL3 0x07
|
||||
#define TPS65090_REG_CG_CTRL4 0x08
|
||||
#define TPS65090_REG_CG_CTRL5 0x09
|
||||
#define TPS65090_REG_CG_STATUS1 0x0a
|
||||
#define TPS65090_REG_CG_STATUS2 0x0b
|
||||
|
||||
struct tps65090 {
|
||||
struct device *dev;
|
||||
struct regmap *rmap;
|
||||
|
|
|
|||
|
|
@ -17,6 +17,8 @@
|
|||
#define TPS658621A 0x15
|
||||
#define TPS658621CD 0x2c
|
||||
#define TPS658623 0x1b
|
||||
#define TPS658640 0x01
|
||||
#define TPS658640v2 0x02
|
||||
#define TPS658643 0x03
|
||||
|
||||
enum {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue