ASoC: Intel: Add Haswell/Broadwell IPC
Add support for Haswell and Broadwell DSP IPC. This is used by the DSP platform PCM driver to configure the DSP for audio operations. Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Liam Girdwood
Mark Brown
parent
1e42c3e426
commit
2298124358
2 changed files with 2273 additions and 0 deletions
1785
sound/soc/intel/sst-haswell-ipc.c
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1785
sound/soc/intel/sst-haswell-ipc.c
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sound/soc/intel/sst-haswell-ipc.h
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sound/soc/intel/sst-haswell-ipc.h
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/*
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* Intel SST Haswell/Broadwell IPC Support
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*
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* Copyright (C) 2013, Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version
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* 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SST_HASWELL_IPC_H
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#define __SST_HASWELL_IPC_H
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#define SST_HSW_NO_CHANNELS 2
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#define SST_HSW_MAX_DX_REGIONS 14
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#define SST_HSW_FW_LOG_CONFIG_DWORDS 12
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#define SST_HSW_GLOBAL_LOG 15
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/**
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* Upfront defined maximum message size that is
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* expected by the in/out communication pipes in FW.
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*/
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#define SST_HSW_IPC_MAX_PAYLOAD_SIZE 400
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#define SST_HSW_MAX_INFO_SIZE 64
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#define SST_HSW_BUILD_HASH_LENGTH 40
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struct sst_hsw;
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struct sst_hsw_stream;
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struct sst_hsw_log_stream;
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struct sst_pdata;
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struct sst_module;
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extern struct sst_ops haswell_ops;
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/* Stream Allocate Path ID */
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enum sst_hsw_stream_path_id {
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SST_HSW_STREAM_PATH_SSP0_OUT = 0,
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SST_HSW_STREAM_PATH_SSP0_IN = 1,
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SST_HSW_STREAM_PATH_MAX_PATH_ID = 2,
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};
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/* Stream Allocate Stream Type */
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enum sst_hsw_stream_type {
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SST_HSW_STREAM_TYPE_RENDER = 0,
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SST_HSW_STREAM_TYPE_SYSTEM = 1,
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SST_HSW_STREAM_TYPE_CAPTURE = 2,
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SST_HSW_STREAM_TYPE_LOOPBACK = 3,
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SST_HSW_STREAM_TYPE_MAX_STREAM_TYPE = 4,
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};
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/* Stream Allocate Stream Format */
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enum sst_hsw_stream_format {
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SST_HSW_STREAM_FORMAT_PCM_FORMAT = 0,
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SST_HSW_STREAM_FORMAT_MP3_FORMAT = 1,
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SST_HSW_STREAM_FORMAT_AAC_FORMAT = 2,
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SST_HSW_STREAM_FORMAT_MAX_FORMAT_ID = 3,
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};
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/* Device ID */
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enum sst_hsw_device_id {
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SST_HSW_DEVICE_SSP_0 = 0,
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SST_HSW_DEVICE_SSP_1 = 1,
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};
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/* Device Master Clock Frequency */
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enum sst_hsw_device_mclk {
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SST_HSW_DEVICE_MCLK_OFF = 0,
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SST_HSW_DEVICE_MCLK_FREQ_6_MHZ = 1,
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SST_HSW_DEVICE_MCLK_FREQ_12_MHZ = 2,
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SST_HSW_DEVICE_MCLK_FREQ_24_MHZ = 3,
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};
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/* Device Clock Master */
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enum sst_hsw_device_mode {
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SST_HSW_DEVICE_CLOCK_SLAVE = 0,
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SST_HSW_DEVICE_CLOCK_MASTER = 1,
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};
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/* DX Power State */
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enum sst_hsw_dx_state {
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SST_HSW_DX_STATE_D0 = 0,
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SST_HSW_DX_STATE_D1 = 1,
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SST_HSW_DX_STATE_D3 = 3,
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SST_HSW_DX_STATE_MAX = 3,
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};
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/* Audio stream stage IDs */
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enum sst_hsw_fx_stage_id {
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SST_HSW_STAGE_ID_WAVES = 0,
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SST_HSW_STAGE_ID_DTS = 1,
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SST_HSW_STAGE_ID_DOLBY = 2,
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SST_HSW_STAGE_ID_BOOST = 3,
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SST_HSW_STAGE_ID_MAX_FX_ID
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};
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/* DX State Type */
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enum sst_hsw_dx_type {
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SST_HSW_DX_TYPE_FW_IMAGE = 0,
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SST_HSW_DX_TYPE_MEMORY_DUMP = 1
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};
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/* Volume Curve Type*/
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enum sst_hsw_volume_curve {
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SST_HSW_VOLUME_CURVE_NONE = 0,
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SST_HSW_VOLUME_CURVE_FADE = 1
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};
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/* Sample ordering */
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enum sst_hsw_interleaving {
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SST_HSW_INTERLEAVING_PER_CHANNEL = 0,
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SST_HSW_INTERLEAVING_PER_SAMPLE = 1,
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};
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/* Channel indices */
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enum sst_hsw_channel_index {
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SST_HSW_CHANNEL_LEFT = 0,
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SST_HSW_CHANNEL_CENTER = 1,
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SST_HSW_CHANNEL_RIGHT = 2,
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SST_HSW_CHANNEL_LEFT_SURROUND = 3,
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SST_HSW_CHANNEL_CENTER_SURROUND = 3,
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SST_HSW_CHANNEL_RIGHT_SURROUND = 4,
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SST_HSW_CHANNEL_LFE = 7,
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SST_HSW_CHANNEL_INVALID = 0xF,
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};
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/* List of supported channel maps. */
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enum sst_hsw_channel_config {
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SST_HSW_CHANNEL_CONFIG_MONO = 0, /* mono only. */
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SST_HSW_CHANNEL_CONFIG_STEREO = 1, /* L & R. */
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SST_HSW_CHANNEL_CONFIG_2_POINT_1 = 2, /* L, R & LFE; PCM only. */
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SST_HSW_CHANNEL_CONFIG_3_POINT_0 = 3, /* L, C & R; MP3 & AAC only. */
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SST_HSW_CHANNEL_CONFIG_3_POINT_1 = 4, /* L, C, R & LFE; PCM only. */
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SST_HSW_CHANNEL_CONFIG_QUATRO = 5, /* L, R, Ls & Rs; PCM only. */
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SST_HSW_CHANNEL_CONFIG_4_POINT_0 = 6, /* L, C, R & Cs; MP3 & AAC only. */
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SST_HSW_CHANNEL_CONFIG_5_POINT_0 = 7, /* L, C, R, Ls & Rs. */
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SST_HSW_CHANNEL_CONFIG_5_POINT_1 = 8, /* L, C, R, Ls, Rs & LFE. */
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SST_HSW_CHANNEL_CONFIG_DUAL_MONO = 9, /* One channel replicated in two. */
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SST_HSW_CHANNEL_CONFIG_INVALID,
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};
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/* List of supported bit depths. */
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enum sst_hsw_bitdepth {
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SST_HSW_DEPTH_8BIT = 8,
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SST_HSW_DEPTH_16BIT = 16,
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SST_HSW_DEPTH_24BIT = 24, /* Default. */
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SST_HSW_DEPTH_32BIT = 32,
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SST_HSW_DEPTH_INVALID = 33,
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};
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enum sst_hsw_module_id {
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SST_HSW_MODULE_BASE_FW = 0x0,
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SST_HSW_MODULE_MP3 = 0x1,
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SST_HSW_MODULE_AAC_5_1 = 0x2,
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SST_HSW_MODULE_AAC_2_0 = 0x3,
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SST_HSW_MODULE_SRC = 0x4,
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SST_HSW_MODULE_WAVES = 0x5,
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SST_HSW_MODULE_DOLBY = 0x6,
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SST_HSW_MODULE_BOOST = 0x7,
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SST_HSW_MODULE_LPAL = 0x8,
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SST_HSW_MODULE_DTS = 0x9,
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SST_HSW_MODULE_PCM_CAPTURE = 0xA,
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SST_HSW_MODULE_PCM_SYSTEM = 0xB,
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SST_HSW_MODULE_PCM_REFERENCE = 0xC,
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SST_HSW_MODULE_PCM = 0xD,
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SST_HSW_MODULE_BLUETOOTH_RENDER_MODULE = 0xE,
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SST_HSW_MODULE_BLUETOOTH_CAPTURE_MODULE = 0xF,
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SST_HSW_MAX_MODULE_ID,
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};
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enum sst_hsw_performance_action {
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SST_HSW_PERF_START = 0,
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SST_HSW_PERF_STOP = 1,
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};
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/* SST firmware module info */
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struct sst_hsw_module_info {
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u8 name[SST_HSW_MAX_INFO_SIZE];
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u8 version[SST_HSW_MAX_INFO_SIZE];
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} __attribute__((packed));
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/* Module entry point */
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struct sst_hsw_module_entry {
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enum sst_hsw_module_id module_id;
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u32 entry_point;
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} __attribute__((packed));
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/* Module map - alignement matches DSP */
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struct sst_hsw_module_map {
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u8 module_entries_count;
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struct sst_hsw_module_entry module_entries[1];
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} __attribute__((packed));
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struct sst_hsw_memory_info {
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u32 offset;
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u32 size;
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} __attribute__((packed));
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struct sst_hsw_fx_enable {
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struct sst_hsw_module_map module_map;
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struct sst_hsw_memory_info persistent_mem;
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} __attribute__((packed));
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struct sst_hsw_get_fx_param {
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u32 parameter_id;
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u32 param_size;
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} __attribute__((packed));
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struct sst_hsw_perf_action {
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u32 action;
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} __attribute__((packed));
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struct sst_hsw_perf_data {
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u64 timestamp;
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u64 cycles;
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u64 datatime;
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} __attribute__((packed));
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/* FW version */
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struct sst_hsw_ipc_fw_version {
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u8 build;
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u8 minor;
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u8 major;
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u8 type;
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u8 fw_build_hash[SST_HSW_BUILD_HASH_LENGTH];
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u32 fw_log_providers_hash;
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} __attribute__((packed));
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/* Stream ring info */
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struct sst_hsw_ipc_stream_ring {
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u32 ring_pt_address;
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u32 num_pages;
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u32 ring_size;
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u32 ring_offset;
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u32 ring_first_pfn;
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} __attribute__((packed));
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/* Debug Dump Log Enable Request */
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struct sst_hsw_ipc_debug_log_enable_req {
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struct sst_hsw_ipc_stream_ring ringinfo;
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u32 config[SST_HSW_FW_LOG_CONFIG_DWORDS];
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} __attribute__((packed));
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/* Debug Dump Log Reply */
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struct sst_hsw_ipc_debug_log_reply {
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u32 log_buffer_begining;
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u32 log_buffer_size;
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} __attribute__((packed));
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/* Stream glitch position */
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struct sst_hsw_ipc_stream_glitch_position {
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u32 glitch_type;
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u32 present_pos;
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u32 write_pos;
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} __attribute__((packed));
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/* Stream get position */
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struct sst_hsw_ipc_stream_get_position {
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u32 position;
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u32 fw_cycle_count;
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} __attribute__((packed));
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/* Stream set position */
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struct sst_hsw_ipc_stream_set_position {
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u32 position;
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u32 end_of_buffer;
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} __attribute__((packed));
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/* Stream Free Request */
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struct sst_hsw_ipc_stream_free_req {
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u8 stream_id;
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u8 reserved[3];
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} __attribute__((packed));
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/* Set Volume Request */
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struct sst_hsw_ipc_volume_req {
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u32 channel;
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u32 target_volume;
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u64 curve_duration;
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u32 curve_type;
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} __attribute__((packed));
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/* Device Configuration Request */
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struct sst_hsw_ipc_device_config_req {
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u32 ssp_interface;
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u32 clock_frequency;
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u32 mode;
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u16 clock_divider;
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u16 reserved;
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} __attribute__((packed));
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/* Audio Data formats */
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struct sst_hsw_audio_data_format_ipc {
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u32 frequency;
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u32 bitdepth;
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u32 map;
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u32 config;
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u32 style;
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u8 ch_num;
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u8 valid_bit;
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u8 reserved[2];
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} __attribute__((packed));
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/* Stream Allocate Request */
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struct sst_hsw_ipc_stream_alloc_req {
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u8 path_id;
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u8 stream_type;
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u8 format_id;
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u8 reserved;
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struct sst_hsw_audio_data_format_ipc format;
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struct sst_hsw_ipc_stream_ring ringinfo;
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struct sst_hsw_module_map map;
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struct sst_hsw_memory_info persistent_mem;
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struct sst_hsw_memory_info scratch_mem;
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u32 number_of_notifications;
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} __attribute__((packed));
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/* Stream Allocate Reply */
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struct sst_hsw_ipc_stream_alloc_reply {
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u32 stream_hw_id;
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u32 mixer_hw_id; // returns rate ????
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u32 read_position_register_address;
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u32 presentation_position_register_address;
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u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
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u32 volume_register_address[SST_HSW_NO_CHANNELS];
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} __attribute__((packed));
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/* Get Mixer Stream Info */
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struct sst_hsw_ipc_stream_info_reply {
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u32 mixer_hw_id;
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u32 peak_meter_register_address[SST_HSW_NO_CHANNELS];
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u32 volume_register_address[SST_HSW_NO_CHANNELS];
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} __attribute__((packed));
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/* DX State Request */
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struct sst_hsw_ipc_dx_req {
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u8 state;
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u8 reserved[3];
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} __attribute__((packed));
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/* DX State Reply Memory Info Item */
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struct sst_hsw_ipc_dx_memory_item {
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u32 offset;
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u32 size;
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u32 source;
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} __attribute__((packed));
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/* DX State Reply */
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struct sst_hsw_ipc_dx_reply {
|
||||||
|
u32 entries_no;
|
||||||
|
struct sst_hsw_ipc_dx_memory_item mem_info[SST_HSW_MAX_DX_REGIONS];
|
||||||
|
} __attribute__((packed));
|
||||||
|
|
||||||
|
struct sst_hsw_ipc_fw_version;
|
||||||
|
|
||||||
|
/* SST Init & Free */
|
||||||
|
struct sst_hsw *sst_hsw_new(struct device *dev, const u8 *fw, size_t fw_length,
|
||||||
|
u32 fw_offset);
|
||||||
|
void sst_hsw_free(struct sst_hsw *hsw);
|
||||||
|
int sst_hsw_fw_get_version(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_ipc_fw_version *version);
|
||||||
|
u32 create_channel_map(enum sst_hsw_channel_config config);
|
||||||
|
|
||||||
|
/* Stream Mixer Controls - */
|
||||||
|
int sst_hsw_stream_mute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
u32 stage_id, u32 channel);
|
||||||
|
int sst_hsw_stream_unmute(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
u32 stage_id, u32 channel);
|
||||||
|
|
||||||
|
int sst_hsw_stream_set_volume(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 volume);
|
||||||
|
int sst_hsw_stream_get_volume(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 stage_id, u32 channel, u32 *volume);
|
||||||
|
|
||||||
|
int sst_hsw_stream_set_volume_curve(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u64 curve_duration,
|
||||||
|
enum sst_hsw_volume_curve curve);
|
||||||
|
|
||||||
|
/* Global Mixer Controls - */
|
||||||
|
int sst_hsw_mixer_mute(struct sst_hsw *hsw, u32 stage_id, u32 channel);
|
||||||
|
int sst_hsw_mixer_unmute(struct sst_hsw *hsw, u32 stage_id, u32 channel);
|
||||||
|
|
||||||
|
int sst_hsw_mixer_set_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
|
||||||
|
u32 volume);
|
||||||
|
int sst_hsw_mixer_get_volume(struct sst_hsw *hsw, u32 stage_id, u32 channel,
|
||||||
|
u32 *volume);
|
||||||
|
|
||||||
|
int sst_hsw_mixer_set_volume_curve(struct sst_hsw *hsw,
|
||||||
|
u64 curve_duration, enum sst_hsw_volume_curve curve);
|
||||||
|
|
||||||
|
/* Stream API */
|
||||||
|
struct sst_hsw_stream *sst_hsw_stream_new(struct sst_hsw *hsw, int id,
|
||||||
|
u32 (*get_write_position)(struct sst_hsw_stream *stream, void *data),
|
||||||
|
void *data);
|
||||||
|
|
||||||
|
int sst_hsw_stream_free(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
|
||||||
|
|
||||||
|
/* Stream Configuration */
|
||||||
|
int sst_hsw_stream_format(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
enum sst_hsw_stream_path_id path_id,
|
||||||
|
enum sst_hsw_stream_type stream_type,
|
||||||
|
enum sst_hsw_stream_format format_id);
|
||||||
|
|
||||||
|
int sst_hsw_stream_buffer(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
u32 ring_pt_address, u32 num_pages,
|
||||||
|
u32 ring_size, u32 ring_offset, u32 ring_first_pfn);
|
||||||
|
|
||||||
|
int sst_hsw_stream_commit(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
|
||||||
|
|
||||||
|
int sst_hsw_stream_set_valid(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
u32 bits);
|
||||||
|
int sst_hsw_stream_set_rate(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
int rate);
|
||||||
|
int sst_hsw_stream_set_bits(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
enum sst_hsw_bitdepth bits);
|
||||||
|
int sst_hsw_stream_set_channels(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, int channels);
|
||||||
|
int sst_hsw_stream_set_map_config(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 map,
|
||||||
|
enum sst_hsw_channel_config config);
|
||||||
|
int sst_hsw_stream_set_style(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
enum sst_hsw_interleaving style);
|
||||||
|
int sst_hsw_stream_set_module_info(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, enum sst_hsw_module_id module_id,
|
||||||
|
u32 entry_point);
|
||||||
|
int sst_hsw_stream_set_pmemory_info(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 offset, u32 size);
|
||||||
|
int sst_hsw_stream_set_smemory_info(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 offset, u32 size);
|
||||||
|
int sst_hsw_stream_get_hw_id(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream);
|
||||||
|
int sst_hsw_stream_get_mixer_id(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream);
|
||||||
|
u32 sst_hsw_stream_get_read_reg(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream);
|
||||||
|
u32 sst_hsw_stream_get_pointer_reg(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream);
|
||||||
|
u32 sst_hsw_stream_get_peak_reg(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 channel);
|
||||||
|
u32 sst_hsw_stream_get_vol_reg(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 channel);
|
||||||
|
int sst_hsw_mixer_get_info(struct sst_hsw *hsw);
|
||||||
|
|
||||||
|
/* Stream ALSA trigger operations */
|
||||||
|
int sst_hsw_stream_pause(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
int wait);
|
||||||
|
int sst_hsw_stream_resume(struct sst_hsw *hsw, struct sst_hsw_stream *stream,
|
||||||
|
int wait);
|
||||||
|
int sst_hsw_stream_reset(struct sst_hsw *hsw, struct sst_hsw_stream *stream);
|
||||||
|
|
||||||
|
/* Stream pointer positions */
|
||||||
|
int sst_hsw_stream_get_read_pos(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 *position);
|
||||||
|
int sst_hsw_stream_get_write_pos(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 *position);
|
||||||
|
int sst_hsw_stream_set_write_position(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream, u32 stage_id, u32 position);
|
||||||
|
int sst_hsw_get_dsp_position(struct sst_hsw *hsw,
|
||||||
|
struct sst_hsw_stream *stream);
|
||||||
|
|
||||||
|
/* HW port config */
|
||||||
|
int sst_hsw_device_set_config(struct sst_hsw *hsw,
|
||||||
|
enum sst_hsw_device_id dev, enum sst_hsw_device_mclk mclk,
|
||||||
|
enum sst_hsw_device_mode mode, u32 clock_divider);
|
||||||
|
|
||||||
|
/* DX Config */
|
||||||
|
int sst_hsw_dx_set_state(struct sst_hsw *hsw,
|
||||||
|
enum sst_hsw_dx_state state, struct sst_hsw_ipc_dx_reply *dx);
|
||||||
|
int sst_hsw_dx_get_state(struct sst_hsw *hsw, u32 item,
|
||||||
|
u32 *offset, u32 *size, u32 *source);
|
||||||
|
|
||||||
|
/* init */
|
||||||
|
int sst_hsw_dsp_init(struct device *dev, struct sst_pdata *pdata);
|
||||||
|
void sst_hsw_dsp_free(struct device *dev, struct sst_pdata *pdata);
|
||||||
|
struct sst_dsp *sst_hsw_get_dsp(struct sst_hsw *hsw);
|
||||||
|
void sst_hsw_set_scratch_module(struct sst_hsw *hsw,
|
||||||
|
struct sst_module *scratch);
|
||||||
|
|
||||||
|
#endif
|
||||||
Loading…
Add table
Add a link
Reference in a new issue