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drm/i915: Rename intel_flush_display_plane to intel_flush_primary_plane

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The intel_flush_primary_plane name actually tells us which plane
we're talking about.

Also reorganize the internals a bit and add a missing POSTING_READ()
to make sure the hardware has seen the changes by the time we
return from the function.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-10-01 18:02:18 +03:00 • committed by Daniel Vetter
commit 1dba99f495
4 changed files with 12 additions and 12 deletions
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14
drivers/gpu/drm/i915/intel_display.c
View file

@ -1812,13 +1812,13 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
* Plane regs are double buffered, going from enabled->disabled needs a * Plane regs are double buffered, going from enabled->disabled needs a
* trigger in order to latch. The display address reg provides this. * trigger in order to latch. The display address reg provides this.
*/ */
void intel_flush_display_plane(struct drm_i915_private *dev_priv, void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane) enum plane plane)
{ {
if (dev_priv->info->gen >= 4) u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
else I915_WRITE(reg, I915_READ(reg));
I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane))); POSTING_READ(reg);
} }
/** /**
@ -1848,7 +1848,7 @@ static void intel_enable_plane(struct drm_i915_private *dev_priv,
return; return;
I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE); I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
intel_flush_display_plane(dev_priv, plane); intel_flush_primary_plane(dev_priv, plane);
intel_wait_for_vblank(dev_priv->dev, pipe); intel_wait_for_vblank(dev_priv->dev, pipe);
} }
@ -1876,7 +1876,7 @@ static void intel_disable_plane(struct drm_i915_private *dev_priv,
return; return;
I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE); I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
intel_flush_display_plane(dev_priv, plane); intel_flush_primary_plane(dev_priv, plane);
intel_wait_for_vblank(dev_priv->dev, pipe); intel_wait_for_vblank(dev_priv->dev, pipe);
} }

2
drivers/gpu/drm/i915/intel_drv.h
View file

@ -811,7 +811,7 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob);
/* intel_sprite.c */ /* intel_sprite.c */
int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane); int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
void intel_flush_display_plane(struct drm_i915_private *dev_priv, void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
enum plane plane); enum plane plane);
void intel_plane_restore(struct drm_plane *plane); void intel_plane_restore(struct drm_plane *plane);
void intel_plane_disable(struct drm_plane *plane); void intel_plane_disable(struct drm_plane *plane);

2
drivers/gpu/drm/i915/intel_pm.c
View file

@ -4773,7 +4773,7 @@ static void g4x_disable_trickle_feed(struct drm_device *dev)
I915_WRITE(DSPCNTR(pipe), I915_WRITE(DSPCNTR(pipe),
I915_READ(DSPCNTR(pipe)) | I915_READ(DSPCNTR(pipe)) |
DISPPLANE_TRICKLE_FEED_DISABLE); DISPPLANE_TRICKLE_FEED_DISABLE);
intel_flush_display_plane(dev_priv, pipe); intel_flush_primary_plane(dev_priv, pipe);
} }
} }

4
drivers/gpu/drm/i915/intel_tv.c
View file

@ -1094,7 +1094,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
unsigned int xsize, ysize; unsigned int xsize, ysize;
/* Pipe must be off here */ /* Pipe must be off here */
I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE); I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
intel_flush_display_plane(dev_priv, intel_crtc->plane); intel_flush_primary_plane(dev_priv, intel_crtc->plane);
/* Wait for vblank for the disable to take effect */ /* Wait for vblank for the disable to take effect */
if (IS_GEN2(dev)) if (IS_GEN2(dev))
@ -1123,7 +1123,7 @@ static void intel_tv_mode_set(struct intel_encoder *encoder)
I915_WRITE(pipeconf_reg, pipeconf); I915_WRITE(pipeconf_reg, pipeconf);
I915_WRITE(dspcntr_reg, dspcntr); I915_WRITE(dspcntr_reg, dspcntr);
intel_flush_display_plane(dev_priv, intel_crtc->plane); intel_flush_primary_plane(dev_priv, intel_crtc->plane);
} }
j = 0; j = 0;