drm/radeon: Only flush HDP cache for indirect buffers from userspace
It isn't necessary for command streams generated by the kernel (at least not while we aren't storing ring or indirect buffers in VRAM). Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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25 changed files with 73 additions and 66 deletions
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@ -107,6 +107,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
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* @rdev: radeon_device pointer
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* @ib: IB object to schedule
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* @const_ib: Const IB to schedule (SI only)
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* @hdp_flush: Whether or not to perform an HDP cache flush
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*
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* Schedule an IB on the associated ring (all asics).
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* Returns 0 on success, error on failure.
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@ -122,7 +123,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
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* to SI there was just a DE IB.
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*/
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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struct radeon_ib *const_ib)
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struct radeon_ib *const_ib, bool hdp_flush)
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{
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struct radeon_ring *ring = &rdev->ring[ib->ring];
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int r = 0;
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@ -176,7 +177,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
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if (ib->vm)
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radeon_vm_fence(rdev, ib->vm, ib->fence);
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radeon_ring_unlock_commit(rdev, ring);
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radeon_ring_unlock_commit(rdev, ring, hdp_flush);
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return 0;
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}
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