Merge branch 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (23 commits) genirq: Expand generic show_interrupts() gpio: Fold irq_set_chip/irq_set_handler to irq_set_chip_and_handler gpio: Cleanup genirq namespace arm: ep93xx: Add basic interrupt info arm/gpio: Remove three copies of broken and racy debug code xtensa: Use generic show_interrupts() xtensa: Convert genirq namespace xtensa: Use generic IRQ Kconfig and set GENERIC_HARDIRQS_NO_DEPRECATED xtensa: Convert s6000 gpio irq_chip to new functions xtensa: Convert main irq_chip to new functions um: Use generic show_interrupts() um: Convert genirq namespace m32r: Use generic show_interrupts() m32r: Convert genirq namespace h8300: Use generic show_interrupts() h8300: Convert genirq namespace avr32: Cleanup eic_set_irq_type() avr32: Use generic show_interrupts() avr: Cleanup genirq namespace avr32: Use generic IRQ config, enable GENERIC_HARDIRQS_NO_DEPRECATED ... Fix up trivial conflict in drivers/gpio/timbgpio.c
This commit is contained in:
Linus Torvalds
commit
0dd61be7ec
40 changed files with 283 additions and 602 deletions
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@ -7,6 +7,9 @@ config ZONE_DMA
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config XTENSA
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def_bool y
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select HAVE_IDE
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select HAVE_GENERIC_HARDIRQS
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select GENERIC_IRQ_SHOW
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select GENERIC_HARDIRQS_NO_DEPRECATED
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help
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Xtensa processors are 32-bit RISC machines designed by Tensilica
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primarily for embedded systems. These processors are both
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@ -27,9 +30,6 @@ config GENERIC_FIND_BIT_LE
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config GENERIC_HWEIGHT
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def_bool y
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config GENERIC_HARDIRQS
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def_bool y
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config GENERIC_GPIO
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def_bool y
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@ -35,7 +35,6 @@ atomic_t irq_err_count;
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asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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struct irq_desc *desc = irq_desc + irq;
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if (irq >= NR_IRQS) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
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@ -57,104 +56,69 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
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sp - sizeof(struct thread_info));
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}
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#endif
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desc->handle_irq(irq, desc);
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generic_handle_irq(irq);
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irq_exit();
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set_irq_regs(old_regs);
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}
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/*
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* Generic, controller-independent functions:
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*/
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int show_interrupts(struct seq_file *p, void *v)
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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int i = *(loff_t *) v, j;
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struct irqaction * action;
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unsigned long flags;
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int j;
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if (i == 0) {
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seq_printf(p, " ");
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for_each_online_cpu(j)
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seq_printf(p, "CPU%d ",j);
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seq_putc(p, '\n');
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}
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if (i < NR_IRQS) {
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raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
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action = irq_desc[i].action;
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if (!action)
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goto skip;
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seq_printf(p, "%3d: ",i);
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#ifndef CONFIG_SMP
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seq_printf(p, "%10u ", kstat_irqs(i));
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#else
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
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#endif
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seq_printf(p, " %14s", irq_desc[i].chip->name);
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seq_printf(p, " %s", action->name);
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for (action=action->next; action; action = action->next)
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seq_printf(p, ", %s", action->name);
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seq_putc(p, '\n');
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skip:
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raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
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} else if (i == NR_IRQS) {
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seq_printf(p, "NMI: ");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", nmi_count(j));
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seq_putc(p, '\n');
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seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
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}
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seq_printf(p, "%*s: ", prec, "NMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", nmi_count(j));
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seq_putc(p, '\n');
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seq_printf(p, "%*s: ", prec, "ERR");
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seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
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return 0;
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}
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static void xtensa_irq_mask(unsigned int irq)
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static void xtensa_irq_mask(struct irq_chip *d)
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{
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cached_irq_mask &= ~(1 << irq);
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cached_irq_mask &= ~(1 << d->irq);
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set_sr (cached_irq_mask, INTENABLE);
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}
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static void xtensa_irq_unmask(unsigned int irq)
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static void xtensa_irq_unmask(struct irq_chip *d)
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{
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cached_irq_mask |= 1 << irq;
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cached_irq_mask |= 1 << d->irq;
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set_sr (cached_irq_mask, INTENABLE);
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}
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static void xtensa_irq_enable(unsigned int irq)
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static void xtensa_irq_enable(struct irq_chip *d)
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{
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variant_irq_enable(irq);
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xtensa_irq_unmask(irq);
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variant_irq_enable(d->irq);
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xtensa_irq_unmask(d->irq);
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}
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static void xtensa_irq_disable(unsigned int irq)
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static void xtensa_irq_disable(struct irq_chip *d)
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{
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xtensa_irq_mask(irq);
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variant_irq_disable(irq);
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xtensa_irq_mask(d->irq);
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variant_irq_disable(d->irq);
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}
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static void xtensa_irq_ack(unsigned int irq)
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static void xtensa_irq_ack(struct irq_chip *d)
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{
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set_sr(1 << irq, INTCLEAR);
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set_sr(1 << d->irq, INTCLEAR);
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}
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static int xtensa_irq_retrigger(unsigned int irq)
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static int xtensa_irq_retrigger(struct irq_chip *d)
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{
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set_sr (1 << irq, INTSET);
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set_sr (1 << d->irq, INTSET);
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return 1;
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}
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static struct irq_chip xtensa_irq_chip = {
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.name = "xtensa",
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.enable = xtensa_irq_enable,
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.disable = xtensa_irq_disable,
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.mask = xtensa_irq_mask,
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.unmask = xtensa_irq_unmask,
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.ack = xtensa_irq_ack,
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.retrigger = xtensa_irq_retrigger,
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.irq_enable = xtensa_irq_enable,
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.irq_disable = xtensa_irq_disable,
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.irq_mask = xtensa_irq_mask,
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.irq_unmask = xtensa_irq_unmask,
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.irq_ack = xtensa_irq_ack,
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.irq_retrigger = xtensa_irq_retrigger,
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};
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void __init init_IRQ(void)
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@ -165,25 +129,25 @@ void __init init_IRQ(void)
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int mask = 1 << index;
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if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
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set_irq_chip_and_handler(index, &xtensa_irq_chip,
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_simple_irq);
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else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
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set_irq_chip_and_handler(index, &xtensa_irq_chip,
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_edge_irq);
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else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
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set_irq_chip_and_handler(index, &xtensa_irq_chip,
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_level_irq);
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else if (mask & XCHAL_INTTYPE_MASK_TIMER)
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set_irq_chip_and_handler(index, &xtensa_irq_chip,
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_edge_irq);
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else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
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/* XCHAL_INTTYPE_MASK_NMI */
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set_irq_chip_and_handler(index, &xtensa_irq_chip,
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irq_set_chip_and_handler(index, &xtensa_irq_chip,
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handle_level_irq);
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}
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@ -120,7 +120,7 @@ static int __init prepare_phy_irq(int pin)
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irq = gpio_to_irq(pin);
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if (irq < 0)
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goto free;
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if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
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if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
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goto free;
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return irq;
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free:
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@ -85,30 +85,29 @@ int s6_gpio_init(u32 afsel)
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return gpiochip_add(&gpiochip);
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}
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static void ack(unsigned int irq)
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static void ack(struct irq_data *d)
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{
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writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
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writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
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}
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static void mask(unsigned int irq)
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static void mask(struct irq_data *d)
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{
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u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
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r &= ~(1 << (irq - IRQ_BASE));
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r &= ~(1 << (d->irq - IRQ_BASE));
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writeb(r, S6_REG_GPIO + S6_GPIO_IE);
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}
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static void unmask(unsigned int irq)
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static void unmask(struct irq_data *d)
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{
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u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
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m |= 1 << (irq - IRQ_BASE);
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m |= 1 << (d->irq - IRQ_BASE);
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writeb(m, S6_REG_GPIO + S6_GPIO_IE);
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}
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static int set_type(unsigned int irq, unsigned int type)
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static int set_type(struct irq_data *d, unsigned int type)
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{
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const u8 m = 1 << (irq - IRQ_BASE);
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const u8 m = 1 << (d->irq - IRQ_BASE);
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irq_flow_handler_t handler;
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struct irq_desc *desc;
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u8 reg;
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if (type == IRQ_TYPE_PROBE) {
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@ -129,8 +128,7 @@ static int set_type(unsigned int irq, unsigned int type)
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handler = handle_edge_irq;
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}
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writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
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desc = irq_to_desc(irq);
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desc->handle_irq = handler;
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__irq_set_handler_locked(irq, handler);
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reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
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if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
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@ -150,22 +148,23 @@ static int set_type(unsigned int irq, unsigned int type)
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static struct irq_chip gpioirqs = {
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.name = "GPIO",
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.ack = ack,
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.mask = mask,
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.unmask = unmask,
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.set_type = set_type,
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.irq_ack = ack,
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.irq_mask = mask,
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.irq_unmask = unmask,
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.irq_set_type = set_type,
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};
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static u8 demux_masks[4];
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static void demux_irqs(unsigned int irq, struct irq_desc *desc)
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{
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u8 *mask = get_irq_desc_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u8 *mask = irq_desc_get_handler_data(desc);
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u8 pending;
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int cirq;
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desc->chip->mask(irq);
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desc->chip->ack(irq);
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chip->irq_mask(&desc->irq_data);
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chip->irq_ack(&desc->irq_data));
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pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
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cirq = IRQ_BASE - 1;
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while (pending) {
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@ -174,7 +173,7 @@ static void demux_irqs(unsigned int irq, struct irq_desc *desc)
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pending >>= n;
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generic_handle_irq(cirq);
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}
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desc->chip->unmask(irq);
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chip->irq_unmask(&desc->irq_data));
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}
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extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
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@ -219,11 +218,11 @@ void __init variant_init_irq(void)
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i = ffs(mask);
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cirq += i;
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mask >>= i;
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set_irq_chip(cirq, &gpioirqs);
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set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
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irq_set_chip(cirq, &gpioirqs);
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irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
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} while (mask);
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set_irq_data(irq, demux_masks + n);
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set_irq_chained_handler(irq, demux_irqs);
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irq_set_handler_data(irq, demux_masks + n);
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irq_set_chained_handler(irq, demux_irqs);
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if (++n == ARRAY_SIZE(demux_masks))
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break;
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}
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