159 lines
		
	
	
	
		
			4.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
		
		
			
		
	
	
			159 lines
		
	
	
	
		
			4.1 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
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								/*
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								 * (not much of an) Emulation layer for 32bit guests.
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								 *
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								 * Copyright (C) 2012,2013 - ARM Ltd
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								 * Author: Marc Zyngier <marc.zyngier@arm.com>
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								 *
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								 * based on arch/arm/kvm/emulate.c
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								 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
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								 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
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								 *
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								 * This program is free software: you can redistribute it and/or modify
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								 * it under the terms of the GNU General Public License version 2 as
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								 * published by the Free Software Foundation.
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								 *
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								 * This program is distributed in the hope that it will be useful,
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								 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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								 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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								 * GNU General Public License for more details.
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								 *
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								 * You should have received a copy of the GNU General Public License
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								 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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								 */
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								#include <linux/kvm_host.h>
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								#include <asm/kvm_emulate.h>
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								/*
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								 * stolen from arch/arm/kernel/opcodes.c
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								 *
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								 * condition code lookup table
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								 * index into the table is test code: EQ, NE, ... LT, GT, AL, NV
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								 *
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								 * bit position in short is condition code: NZCV
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								 */
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								static const unsigned short cc_map[16] = {
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									0xF0F0,			/* EQ == Z set            */
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									0x0F0F,			/* NE                     */
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									0xCCCC,			/* CS == C set            */
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									0x3333,			/* CC                     */
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									0xFF00,			/* MI == N set            */
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									0x00FF,			/* PL                     */
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									0xAAAA,			/* VS == V set            */
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									0x5555,			/* VC                     */
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									0x0C0C,			/* HI == C set && Z clear */
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									0xF3F3,			/* LS == C clear || Z set */
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									0xAA55,			/* GE == (N==V)           */
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									0x55AA,			/* LT == (N!=V)           */
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									0x0A05,			/* GT == (!Z && (N==V))   */
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									0xF5FA,			/* LE == (Z || (N!=V))    */
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									0xFFFF,			/* AL always              */
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									0			/* NV                     */
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								};
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								static int kvm_vcpu_get_condition(const struct kvm_vcpu *vcpu)
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								{
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									u32 esr = kvm_vcpu_get_hsr(vcpu);
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									if (esr & ESR_EL2_CV)
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										return (esr & ESR_EL2_COND) >> ESR_EL2_COND_SHIFT;
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									return -1;
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								}
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								/*
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								 * Check if a trapped instruction should have been executed or not.
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								 */
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								bool kvm_condition_valid32(const struct kvm_vcpu *vcpu)
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								{
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									unsigned long cpsr;
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									u32 cpsr_cond;
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									int cond;
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									/* Top two bits non-zero?  Unconditional. */
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									if (kvm_vcpu_get_hsr(vcpu) >> 30)
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										return true;
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									/* Is condition field valid? */
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									cond = kvm_vcpu_get_condition(vcpu);
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									if (cond == 0xE)
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										return true;
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									cpsr = *vcpu_cpsr(vcpu);
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									if (cond < 0) {
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										/* This can happen in Thumb mode: examine IT state. */
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										unsigned long it;
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										it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
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										/* it == 0 => unconditional. */
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										if (it == 0)
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											return true;
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										/* The cond for this insn works out as the top 4 bits. */
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										cond = (it >> 4);
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									}
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									cpsr_cond = cpsr >> 28;
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									if (!((cc_map[cond] >> cpsr_cond) & 1))
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										return false;
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									return true;
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								}
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								/**
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								 * adjust_itstate - adjust ITSTATE when emulating instructions in IT-block
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								 * @vcpu:	The VCPU pointer
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								 *
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								 * When exceptions occur while instructions are executed in Thumb IF-THEN
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								 * blocks, the ITSTATE field of the CPSR is not advanced (updated), so we have
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								 * to do this little bit of work manually. The fields map like this:
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								 *
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								 * IT[7:0] -> CPSR[26:25],CPSR[15:10]
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								 */
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								static void kvm_adjust_itstate(struct kvm_vcpu *vcpu)
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								{
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									unsigned long itbits, cond;
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									unsigned long cpsr = *vcpu_cpsr(vcpu);
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									bool is_arm = !(cpsr & COMPAT_PSR_T_BIT);
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									BUG_ON(is_arm && (cpsr & COMPAT_PSR_IT_MASK));
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									if (!(cpsr & COMPAT_PSR_IT_MASK))
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										return;
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									cond = (cpsr & 0xe000) >> 13;
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									itbits = (cpsr & 0x1c00) >> (10 - 2);
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									itbits |= (cpsr & (0x3 << 25)) >> 25;
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									/* Perform ITAdvance (see page A2-52 in ARM DDI 0406C) */
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									if ((itbits & 0x7) == 0)
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										itbits = cond = 0;
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									else
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										itbits = (itbits << 1) & 0x1f;
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									cpsr &= ~COMPAT_PSR_IT_MASK;
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									cpsr |= cond << 13;
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									cpsr |= (itbits & 0x1c) << (10 - 2);
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									cpsr |= (itbits & 0x3) << 25;
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									*vcpu_cpsr(vcpu) = cpsr;
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								}
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								/**
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								 * kvm_skip_instr - skip a trapped instruction and proceed to the next
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								 * @vcpu: The vcpu pointer
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								 */
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								void kvm_skip_instr32(struct kvm_vcpu *vcpu, bool is_wide_instr)
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								{
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									bool is_thumb;
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									is_thumb = !!(*vcpu_cpsr(vcpu) & COMPAT_PSR_T_BIT);
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									if (is_thumb && !is_wide_instr)
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										*vcpu_pc(vcpu) += 2;
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									else
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										*vcpu_pc(vcpu) += 4;
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									kvm_adjust_itstate(vcpu);
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								}
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