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								/*
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								 * arch/arm/plat-omap/include/mach/aic23.h
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								 *
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								 * Hardware definitions for TI TLV320AIC23 audio codec
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								 * Copyright (C) 2002 RidgeRun, Inc.
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								 * Author: Steve Johnson
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								 *
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								 * This program is free software; you can redistribute it and/or modify it
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								 * under the terms of the GNU General Public License as published by the
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								 * Free Software Foundation; either version 2 of the License, or (at your
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								 * option) any later version.
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								 *
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								 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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								 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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								 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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								 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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								 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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								 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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								 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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								 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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								 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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								 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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								 *
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								 * You should have received a copy of the  GNU General Public License along
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								 * with this program; if not, write  to the Free Software Foundation, Inc.,
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								 * 675 Mass Ave, Cambridge, MA 02139, USA.
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								 */
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								#ifndef __ASM_ARCH_AIC23_H
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								#define __ASM_ARCH_AIC23_H
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								// Codec TLV320AIC23
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								#define LEFT_LINE_VOLUME_ADDR		0x00
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								#define RIGHT_LINE_VOLUME_ADDR		0x01
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								#define LEFT_CHANNEL_VOLUME_ADDR	0x02
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								#define RIGHT_CHANNEL_VOLUME_ADDR	0x03
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								#define ANALOG_AUDIO_CONTROL_ADDR	0x04
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								#define DIGITAL_AUDIO_CONTROL_ADDR	0x05
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								#define POWER_DOWN_CONTROL_ADDR		0x06
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								#define DIGITAL_AUDIO_FORMAT_ADDR	0x07
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								#define SAMPLE_RATE_CONTROL_ADDR	0x08
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								#define DIGITAL_INTERFACE_ACT_ADDR	0x09
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								#define RESET_CONTROL_ADDR		0x0F
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								// Left (right) line input volume control register
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								#define LRS_ENABLED			0x0100
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								#define LIM_MUTED			0x0080
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								#define LIV_DEFAULT			0x0017
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								#define LIV_MAX				0x001f
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								#define LIV_MIN				0x0000
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								// Left (right) channel headphone volume control register
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								#define LZC_ON				0x0080
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								#define LHV_DEFAULT			0x0079
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								#define LHV_MAX				0x007f
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								#define LHV_MIN				0x0000
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								// Analog audio path control register
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								#define STA_REG(x)			((x)<<6)
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								#define STE_ENABLED			0x0020
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								#define DAC_SELECTED			0x0010
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								#define BYPASS_ON			0x0008
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								#define INSEL_MIC			0x0004
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								#define MICM_MUTED			0x0002
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								#define MICB_20DB			0x0001
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								// Digital audio path control register
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								#define DACM_MUTE			0x0008
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								#define DEEMP_32K			0x0002
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								#define DEEMP_44K			0x0004
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								#define DEEMP_48K			0x0006
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								#define ADCHP_ON			0x0001
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								// Power control down register
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								#define DEVICE_POWER_OFF	  	0x0080
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								#define CLK_OFF				0x0040
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								#define OSC_OFF				0x0020
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								#define OUT_OFF				0x0010
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								#define DAC_OFF				0x0008
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								#define ADC_OFF				0x0004
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								#define MIC_OFF				0x0002
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								#define LINE_OFF			0x0001
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								// Digital audio interface register
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								#define MS_MASTER			0x0040
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								#define LRSWAP_ON			0x0020
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								#define LRP_ON				0x0010
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								#define IWL_16				0x0000
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								#define IWL_20				0x0004
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								#define IWL_24				0x0008
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								#define IWL_32				0x000C
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								#define FOR_I2S				0x0002
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								#define FOR_DSP				0x0003
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								// Sample rate control register
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								#define CLKOUT_HALF			0x0080
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								#define CLKIN_HALF			0x0040
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								#define BOSR_384fs			0x0002 // BOSR_272fs when in USB mode
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								#define USB_CLK_ON			0x0001
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								#define SR_MASK                         0xf
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								#define CLKOUT_SHIFT                    7
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								#define CLKIN_SHIFT                     6
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								#define SR_SHIFT                        2
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								#define BOSR_SHIFT                      1
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								// Digital interface register
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								#define ACT_ON				0x0001
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								#define TLV320AIC23ID1                  (0x1a)	// cs low
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								#define TLV320AIC23ID2                  (0x1b)	// cs high
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								void aic23_power_up(void);
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								void aic23_power_down(void);
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								#endif /* __ASM_ARCH_AIC23_H */
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