| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * PKUnity Ultra Media Access Layer (UMAL) Ethernet MAC Registers | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /* MAC module of UMAL */ | 
					
						
							|  |  |  | /* UMAL's MAC module includes G/MII interface, several additional PHY
 | 
					
						
							|  |  |  |  * interfaces, and MAC control sub-layer, which provides support for control | 
					
						
							|  |  |  |  * frames (e.g. PAUSE frames). | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * TX/RX reset and control UMAL_CFG1 | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_CFG1		(PKUNITY_UMAL_BASE + 0x0000)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MAC interface mode control UMAL_CFG2 | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_CFG2		(PKUNITY_UMAL_BASE + 0x0004)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Inter Packet/Frame Gap UMAL_IPGIFG | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_IPGIFG		(PKUNITY_UMAL_BASE + 0x0008)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Collision retry or backoff UMAL_HALFDUPLEX | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_HALFDUPLEX		(PKUNITY_UMAL_BASE + 0x000c)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Maximum Frame Length UMAL_MAXFRAME | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_MAXFRAME		(PKUNITY_UMAL_BASE + 0x0010)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Test Regsiter UMAL_TESTREG | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_TESTREG		(PKUNITY_UMAL_BASE + 0x001c)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MII Management Configure UMAL_MIICFG | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_MIICFG		(PKUNITY_UMAL_BASE + 0x0020)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MII Management Command UMAL_MIICMD | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_MIICMD		(PKUNITY_UMAL_BASE + 0x0024)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MII Management Address UMAL_MIIADDR | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_MIIADDR		(PKUNITY_UMAL_BASE + 0x0028)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MII Management Control UMAL_MIICTRL | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_MIICTRL		(PKUNITY_UMAL_BASE + 0x002c)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MII Management Status UMAL_MIISTATUS | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_MIISTATUS		(PKUNITY_UMAL_BASE + 0x0030)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							| 
									
										
										
										
											2011-03-30 22:57:33 -03:00
										 |  |  |  * MII Management Indicator UMAL_MIIIDCT | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_MIIIDCT		(PKUNITY_UMAL_BASE + 0x0034)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Interface Control UMAL_IFCTRL | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_IFCTRL		(PKUNITY_UMAL_BASE + 0x0038)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Interface Status UMAL_IFSTATUS | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_IFSTATUS		(PKUNITY_UMAL_BASE + 0x003c)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MAC address (high 4 bytes) UMAL_STADDR1 | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_STADDR1		(PKUNITY_UMAL_BASE + 0x0040)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * MAC address (low 2 bytes) UMAL_STADDR2 | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_STADDR2		(PKUNITY_UMAL_BASE + 0x0044)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | 
 | 
					
						
							|  |  |  | /* FIFO MODULE OF UMAL */ | 
					
						
							|  |  |  | /* UMAL's FIFO module provides data queuing for increased system level
 | 
					
						
							|  |  |  |  * throughput | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_FIFOCFG0		(PKUNITY_UMAL_BASE + 0x0048)
 | 
					
						
							|  |  |  | #define UMAL_FIFOCFG1		(PKUNITY_UMAL_BASE + 0x004c)
 | 
					
						
							|  |  |  | #define UMAL_FIFOCFG2		(PKUNITY_UMAL_BASE + 0x0050)
 | 
					
						
							|  |  |  | #define UMAL_FIFOCFG3		(PKUNITY_UMAL_BASE + 0x0054)
 | 
					
						
							|  |  |  | #define UMAL_FIFOCFG4		(PKUNITY_UMAL_BASE + 0x0058)
 | 
					
						
							|  |  |  | #define UMAL_FIFOCFG5		(PKUNITY_UMAL_BASE + 0x005c)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM0		(PKUNITY_UMAL_BASE + 0x0060)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM1		(PKUNITY_UMAL_BASE + 0x0064)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM2		(PKUNITY_UMAL_BASE + 0x0068)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM3		(PKUNITY_UMAL_BASE + 0x006c)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM4		(PKUNITY_UMAL_BASE + 0x0070)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM5		(PKUNITY_UMAL_BASE + 0x0074)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM6		(PKUNITY_UMAL_BASE + 0x0078)
 | 
					
						
							|  |  |  | #define UMAL_FIFORAM7		(PKUNITY_UMAL_BASE + 0x007c)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2011-03-30 22:57:33 -03:00
										 |  |  | /* MAHBE MODULE OF UMAL */ | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /* UMAL's MAHBE module interfaces to the host system through 32-bit AHB Master
 | 
					
						
							|  |  |  |  * and Slave ports.Registers within the M-AHBE provide Control and Status | 
					
						
							|  |  |  |  * information concerning these transfers. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Transmit Control UMAL_DMATxCtrl | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMATxCtrl		(PKUNITY_UMAL_BASE + 0x0180)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Pointer to TX Descripter UMAL_DMATxDescriptor | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMATxDescriptor	(PKUNITY_UMAL_BASE + 0x0184)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Status of Tx Packet Transfers UMAL_DMATxStatus | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMATxStatus	(PKUNITY_UMAL_BASE + 0x0188)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Receive Control UMAL_DMARxCtrl | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMARxCtrl		(PKUNITY_UMAL_BASE + 0x018c)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Pointer to Rx Descriptor UMAL_DMARxDescriptor | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMARxDescriptor	(PKUNITY_UMAL_BASE + 0x0190)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Status of Rx Packet Transfers UMAL_DMARxStatus | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMARxStatus	(PKUNITY_UMAL_BASE + 0x0194)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Interrupt Mask UMAL_DMAIntrMask | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMAIntrMask	(PKUNITY_UMAL_BASE + 0x0198)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Interrupts, read only UMAL_DMAInterrupt | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-03-04 18:07:48 +08:00
										 |  |  | #define UMAL_DMAInterrupt	(PKUNITY_UMAL_BASE + 0x019c)
 | 
					
						
							| 
									
										
										
										
											2011-02-26 20:08:36 +08:00
										 |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Commands for UMAL_CFG1 register | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_CFG1_TXENABLE	FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | #define UMAL_CFG1_RXENABLE	FIELD(1, 1, 2)
 | 
					
						
							|  |  |  | #define UMAL_CFG1_TXFLOWCTL	FIELD(1, 1, 4)
 | 
					
						
							|  |  |  | #define UMAL_CFG1_RXFLOWCTL	FIELD(1, 1, 5)
 | 
					
						
							|  |  |  | #define UMAL_CFG1_CONFLPBK	FIELD(1, 1, 8)
 | 
					
						
							|  |  |  | #define UMAL_CFG1_RESET		FIELD(1, 1, 31)
 | 
					
						
							|  |  |  | #define UMAL_CFG1_CONFFLCTL	(MAC_TX_FLOW_CTL | MAC_RX_FLOW_CTL)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Commands for UMAL_CFG2 register | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_CFG2_FULLDUPLEX	FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_CRCENABLE	FIELD(1, 1, 1)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_PADCRC	FIELD(1, 1, 2)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_LENGTHCHECK	FIELD(1, 1, 4)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_MODEMASK	FMASK(2, 8)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_NIBBLEMODE	FIELD(1, 2, 8)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_BYTEMODE	FIELD(2, 2, 8)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_PREAMBLENMASK	FMASK(4, 12)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_DEFPREAMBLEN	FIELD(7, 4, 12)
 | 
					
						
							|  |  |  | #define UMAL_CFG2_FD100		(UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
 | 
					
						
							|  |  |  | 				| UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \ | 
					
						
							|  |  |  | 				| UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX) | 
					
						
							|  |  |  | #define UMAL_CFG2_FD1000	(UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_BYTEMODE \
 | 
					
						
							|  |  |  | 				| UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \ | 
					
						
							|  |  |  | 				| UMAL_CFG2_CRCENABLE | UMAL_CFG2_FULLDUPLEX) | 
					
						
							|  |  |  | #define UMAL_CFG2_HD100		(UMAL_CFG2_DEFPREAMBLEN | UMAL_CFG2_NIBBLEMODE \
 | 
					
						
							|  |  |  | 				| UMAL_CFG2_LENGTHCHECK | UMAL_CFG2_PADCRC \ | 
					
						
							|  |  |  | 				| UMAL_CFG2_CRCENABLE) | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Command for UMAL_IFCTRL register | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_IFCTRL_RESET	FIELD(1, 1, 31)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Command for UMAL_MIICFG register | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_MIICFG_RESET	FIELD(1, 1, 31)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Command for UMAL_MIICMD register | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_MIICMD_READ	FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Command for UMAL_MIIIDCT register | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_MIIIDCT_BUSY	FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | #define UMAL_MIIIDCT_NOTVALID	FIELD(1, 1, 2)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Commands for DMATxCtrl regesters | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_DMA_Enable		FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Commands for DMARxCtrl regesters | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_DMAIntrMask_ENABLEHALFWORD	FIELD(1, 1, 16)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Command for DMARxStatus | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define CLR_RX_BUS_ERR		FIELD(1, 1, 3)
 | 
					
						
							|  |  |  | #define CLR_RX_OVERFLOW		FIELD(1, 1, 2)
 | 
					
						
							|  |  |  | #define CLR_RX_PKT		FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Command for DMATxStatus | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define CLR_TX_BUS_ERR		FIELD(1, 1, 3)
 | 
					
						
							|  |  |  | #define CLR_TX_UNDERRUN		FIELD(1, 1, 1)
 | 
					
						
							|  |  |  | #define CLR_TX_PKT		FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Commands for DMAIntrMask and DMAInterrupt register | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define INT_RX_MASK		FIELD(0xd, 4, 4)
 | 
					
						
							|  |  |  | #define INT_TX_MASK		FIELD(0xb, 4, 0)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #define INT_RX_BUS_ERR		FIELD(1, 1, 7)
 | 
					
						
							|  |  |  | #define INT_RX_OVERFLOW		FIELD(1, 1, 6)
 | 
					
						
							|  |  |  | #define INT_RX_PKT		FIELD(1, 1, 4)
 | 
					
						
							|  |  |  | #define INT_TX_BUS_ERR		FIELD(1, 1, 3)
 | 
					
						
							|  |  |  | #define INT_TX_UNDERRUN		FIELD(1, 1, 1)
 | 
					
						
							|  |  |  | #define INT_TX_PKT		FIELD(1, 1, 0)
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * MARCOS of UMAL's descriptors | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define UMAL_DESC_PACKETSIZE_EMPTY	FIELD(1, 1, 31)
 | 
					
						
							|  |  |  | #define UMAL_DESC_PACKETSIZE_NONEMPTY	FIELD(0, 1, 31)
 | 
					
						
							|  |  |  | #define UMAL_DESC_PACKETSIZE_SIZEMASK	FMASK(12, 0)
 | 
					
						
							|  |  |  | 
 |