forge/linux-pinenote
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
linux-pinenote/arch/arm/mach-shmobile/include/mach/common.h

104 lines
3.4 KiB
C
Raw Normal View History

ARM: mach-shmobile: SH-Mobile G3 support. This adds preliminary support for the SH-Mobile G-series. The SH-Mobile G-series is a series of ARM/SH multi-core CPUs that aside from the ARM MPU are primarily composed of existing SH IP blocks. This includes initial support for the SH7367 (SH-Mobile G3) CPU and the G3EVM reference board. Only timer, serial console, and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-05 11:14:49 +00:00
#ifndef __ARCH_MACH_COMMON_H
#define __ARCH_MACH_COMMON_H
ARM: mach-shmobile: add shmobile_earlytimer_init() Add shmobile_earlytimer_init() that can be used to enable the earlytimer probing from the SoC code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-03-06 17:36:14 +09:00
extern void shmobile_earlytimer_init(void);
ARM: delete struct sys_timer Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-08 12:40:59 -07:00
extern void shmobile_timer_init(void);
ARM: mach-shmobile: Introduce shmobile_setup_delay() Add the function shmobile_setup_delay() to let platforms configure their maximum loops per jiffy delay. With this jiffies calculation done the dependency on early timer is removed. In the future this allows us to assign timers using the regular driver model via the device tree. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-03-28 19:22:30 +09:00
extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
ARM: SoC: convert shmobile SMP to SMP operations Convert shmobile SMP platforms to use struct smp_operations to provide their SMP and CPU hotplug operations. Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2011-09-08 13:15:22 +01:00
unsigned int mult, unsigned int div);
ARM: shmobile: convert to twd_local_timer_register() interface Add support for the new smp_twd runtime registration interface to the shmobile platforms, and remove the old compile-time support. Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2012-01-10 19:44:19 +00:00
struct twd_local_timer;
ARM: mach-shmobile: early console support using earlyprintk Add support for early console to the SH-Mobile boards. Simply perform an early platform probe for "earlyprintk" to trigger the early serial console code in sh-sci.c. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-08 11:02:54 +00:00
extern void shmobile_setup_console(void);
ARM: mach-shmobile: SMP base support Add SMP base support for R-Mobile / SH-Mobile processors. This patch contains all base code to support CONFIG_SMP regardless of ARCH_SHMOBILE processor type. Both local timer and CPU hotplug are supported, but no processor specific code is included. At this point only the default behavior is in place, so a single core will always be used even though CONFIG_SMP is enabled on multicore systems. The SMP Kconfig entry for arch/arm/Kconfig is excluded from this patch to simplify merging. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-14 16:56:55 +09:00
extern void shmobile_secondary_vector(void);
ARM: mach-shmobile: sh7372 clock fixes Fixes for the sh7372 clock framework: - remove unused #include <linux/platform_device.h> - add sh7372 prefix to user modifiable root clocks - put modifiable root clock prototypes in header file - fix off-by-one id error on VEU MSTP clocks - make arrays static Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-05-20 14:45:03 +00:00
struct clk;
ARM: mach-shmobile: rename clk_init() to shmobile_clk_init() Rename clk_init() to shmobile_clk_init() to avoid a potential future name space collision with the common clock framework. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-02-29 21:41:30 +09:00
extern int shmobile_clk_init(void);
ARM: mach-shmobile: Run-time IRQ handler for INTCA Break-out INTC specific IRQ demux code from the file entry-macro-intc.S and register during run-time. Covers sh7367, sh7377 and sh7372. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-28 08:27:01 +00:00
extern void shmobile_handle_irq_intc(struct pt_regs *);
ARM: mach-shmobile: Suspend-to-RAM support This patch adds a simple Suspend-to-RAM implementation for SH-Mobile ARM. The struct shmobile_suspend_ops are kept global to allow cpu-specific code to override the callbacks if needed. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-04-29 02:23:28 +09:00
extern struct platform_suspend_ops shmobile_suspend_ops;
ARM: mach-shmobile: cpuidle single/global and last_state fixes The following commits break cpuidle on SH-Mobile ARM: 46bcfad cpuidle: Single/Global registration of idle states e978aa7 cpuidle: Move dev->last_residency update to driver enter routine; remove dev->last_state This patch remedies these issues by up-porting the SH-Mobile code to fit with the above introduced framework changes. It is worth noting that the new code becomes significantly cleaner, so these framework changes are very welcome. At the same time this breakage could probably have been avoided by grepping for "last_state" and "cpuidle_register_driver". Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-11-11 14:01:30 +09:00
struct cpuidle_driver;
ARM: shmobile: Make sh7372 cpuidle handling more straightforward The sh7372 cpuidle code uses the same artificially designed routine shmobile_cpuidle_enter() as the .enter() callback for all of its cpuidle states. However, shmobile_cpuidle_enter() calls a different "enter" function for each state using an array of function pointers populated by the sh7372 PM initialization code. Moreover, the states[] array of the shmobile cpuidle driver is populated by that code as well, although in principle it just might have been filled with static data. All of that complexity goes away if the sh7372 cpuidle code is allowed to define its own cpuidle driver structure that can be passed for registration to the common shmobile cpuidle initialization routine, so modify the code accordingly. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Magnus Damm <damm@opensource.se>
2012-08-15 20:58:19 +02:00
struct cpuidle_device;
extern int shmobile_enter_wfi(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);
extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
ARM: mach-shmobile: Use shared clock framework Teach SH-Mobile ARM how to make use of the shared SH clock framework. This commit is one atomic switch that dumps the local hackery and instead links in the shared clock framework code in drivers/sh. A few local functions are kept in clock.c. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-05-12 14:21:24 +00:00
ARM: mach-shmobile: SH-Mobile AP4 support. This adds preliminary support for the SH7372 (SH-Mobile AP4) CPU and the AP4EVB reference board. Only timer, serial console and NOR flash are supported at this point. Support for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-05 11:14:58 +00:00
extern void sh7372_init_irq(void);
ARM: mach-shmobile: sh7372 map_io and init_early update Update the sh7372 SoC and the AP4EVB and Mackerel boards to make use of the functions sh7372_map_io() and sh7372_add_early_devices(). Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-02-29 21:37:19 +09:00
extern void sh7372_map_io(void);
ARM: delete struct sys_timer Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-08 12:40:59 -07:00
extern void sh7372_earlytimer_init(void);
ARM: mach-shmobile: SH-Mobile AP4 support. This adds preliminary support for the SH7372 (SH-Mobile AP4) CPU and the AP4EVB reference board. Only timer, serial console and NOR flash are supported at this point. Support for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-05 11:14:58 +00:00
extern void sh7372_add_early_devices(void);
extern void sh7372_add_standard_devices(void);
ARM: shmobile: add function declarations for sh7372 DT helper functions sh7372_add_early_devices_dt() and sh7372_add_standard_devices_dt() are defined as global functions in arch/arm/mach-shmobile/setup-sh7372.c, but their declarations are missing. Add them to common.h, where similar functions for this and other SoC types are already declared. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms@verge.net.au>
2012-12-31 11:23:50 +00:00
extern void sh7372_add_early_devices_dt(void);
extern void sh7372_add_standard_devices_dt(void);
ARM: mach-shmobile: sh7372 clock framework support V2 This patch is V2 of clock framework tables/code for sh7372. MSTP are included for KEYSC, SCIF, IIC, USB, SDHI and UIO. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-05-12 14:21:34 +00:00
extern void sh7372_clock_init(void);
ARM: mach-shmobile: Add sh7372 pinmux support Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-17 09:39:10 +00:00
extern void sh7372_pinmux_init(void);
ARM: mach-shmobile: sh7372 Core Standby Suspend-to-RAM Add sh7372 Core Standby sleep mode support and tie it in with the shared SH-Mobile ARM suspend code. The Core Standby mode is the lightest sh7372-specific sleep mode, cutting power to the ARM core excluding the L2 cache. Any interrupt source can be used for wakeups. The low level portion of this code is based on the TI OMAP sleep code in sleep34xx.S, thanks to them. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-04-29 02:28:08 +09:00
extern void sh7372_pm_init(void);
PM / shmobile: Add support for the sh7372 A4S power domain / sleep mode The sh7372 contains a power domain named A4S which in turn contains power domains for both I/O Devices and CPU cores. At this point only System wide Suspend-to-RAM is supported, but the the hardware can also support CPUIdle. With more efforts in the future CPUIdle can work with bot A4S and A3SM. Tested on the sh7372 Mackerel board. [rjw: Rebased on top of the current linux-pm tree.] Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2011-12-23 01:23:07 +01:00
extern void sh7372_resume_core_standby_sysc(void);
extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
ARM: mach-shmobile: sh7372 clock fixes Fixes for the sh7372 clock framework: - remove unused #include <linux/platform_device.h> - add sh7372 prefix to user modifiable root clocks - put modifiable root clock prototypes in header file - fix off-by-one id error on VEU MSTP clocks - make arrays static Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-05-20 14:45:03 +00:00
extern struct clk sh7372_extal1_clk;
extern struct clk sh7372_extal2_clk;
ARM: mach-shmobile: SH-Mobile AP4 support. This adds preliminary support for the SH7372 (SH-Mobile AP4) CPU and the AP4EVB reference board. Only timer, serial console and NOR flash are supported at this point. Support for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-05 11:14:58 +00:00
ARM: mach-shmobile: sh73a0 INTCS support Add INTCS support for the sh73a0 processor. The interrupts on the sh73a0 processor are managed through controllers such as GIC, INTCS and INTCA. The ARM cores use the GIC as primary interrupt controller and the INTCS and INTCA are hanging off the GIC as cascaded interrupt controllers. Peripherals connected both to the GIC and the INTC controllers should if possible only use the GIC. If no GIC connection is available then INTCS and INTCA may be used instead. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-21 08:37:32 +00:00
extern void sh73a0_init_irq(void);
ARM: mach-shmobile: sh73a0: Allow initialisation of GIC by DT This allows the GIC interrupt controller of the sh73a0 SoC to be initialised using a flattened device tree blob. It does not allow the INTC interrupt controller which is also present on the sh73a0 SoC to be enabled via device tree. Nor does it handle sharing of interrupts between the GIC and INTC interrupt controllers. This limits the usefulness of this code to applications which only wish to access devices which use interrupts that can be handled by the GIC interrupt controller. Other applications should, for now, continue using non-device tree initialisation of the sh72a0 interrupt controllers. Includes update to use irqchip_init() by Thierry Reding Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-11-21 21:12:43 +09:00
extern void sh73a0_init_irq_dt(void);
ARM: mach-shmobile: sh73a0 map_io and init_early update Update the sh73a0 SoC and the AG5EVM and Kota2 boards to make use of the functions sh73a0_map_io() and sh73a0_add_early_devices(). Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-02-29 21:37:27 +09:00
extern void sh73a0_map_io(void);
ARM: delete struct sys_timer Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-08 12:40:59 -07:00
extern void sh73a0_earlytimer_init(void);
ARM: mach-shmobile: Initial AG5 and AG5EVM support This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-17 10:59:31 +00:00
extern void sh73a0_add_early_devices(void);
ARM: mach-shmobile: sh73a0: Minimal setup using DT Allow a minimal setup of the sh73a0 SoC using a flattened device tree. In particular, Configure the i2c controllers using a flattened device tree. SCI serial controller and CMT clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC. *** Please note that the clock initialisation scheme used in this patch does not currently work with SMP as there is a yet to be resolved lock-up in workqueue initialisation. CONFIG_SMP must be disabled when using this code. *** Includes update from Thierry Reding to no longer use gic_handle_irq() Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> fix
2012-11-21 22:00:15 +09:00
extern void sh73a0_add_early_devices_dt(void);
ARM: mach-shmobile: Initial AG5 and AG5EVM support This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-17 10:59:31 +00:00
extern void sh73a0_add_standard_devices(void);
ARM: mach-shmobile: sh73a0: Minimal setup using DT Allow a minimal setup of the sh73a0 SoC using a flattened device tree. In particular, Configure the i2c controllers using a flattened device tree. SCI serial controller and CMT clock source, whose drivers do not yet support configuration using a flattened device tree, are still configured using C code in order to allow booting of a board with this SoC. *** Please note that the clock initialisation scheme used in this patch does not currently work with SMP as there is a yet to be resolved lock-up in workqueue initialisation. CONFIG_SMP must be disabled when using this code. *** Includes update from Thierry Reding to no longer use gic_handle_irq() Cc: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> fix
2012-11-21 22:00:15 +09:00
extern void sh73a0_add_standard_devices_dt(void);
ARM: mach-shmobile: Initial AG5 and AG5EVM support This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-17 10:59:31 +00:00
extern void sh73a0_clock_init(void);
ARM: mach-shmobile: Add sh73a0 pinmux support PFC definitions for sh73a0 to support GPIO and pinmux handling. Signed-off-by: Takashi YOSHII <takashi.yoshii.zj@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-19 16:47:16 +09:00
extern void sh73a0_pinmux_init(void);
ARM: shmobile: sh73a0: Add CPU sleep suspend Add the lighest possible sleep mode on Cortex-A9 cores: CPU sleep. It is entered by a simple dsb and wfi instruction via cpu_do_idle(). As just clocks are stopped there is no need to save or restore any state of the system. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-12-05 12:13:06 +00:00
extern void sh73a0_pm_init(void);
ARM: SH-Mobile: sh73a0: Secondary CPUs handle own SCU flags When booting secondary CPUs we have used the main CPU to set up the Snoop Control Unit flags of these CPUs. It is a cleaner approach if every CPU takes care of its own flags. We avoid the need for locking and the program logic is more concise. With this patch the file headsmp-sh73a0.S is added that contains a startup vector for secondary CPUs that sets up its own SCU flags. Further in sh73a0_smp_prepare_cpus() we can rely on the generic ARM helper scu_power_mode(). This is possible as we don't cross borders anymore (every CPU handles its own flags) and need no locking. So we can throw out the needless function modify_scu_cpu_psr(). Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-09 19:41:51 +00:00
extern void sh73a0_secondary_vector(void);
ARM: mach-shmobile: AG5 clock framework improvements This patch improves the state of the AG5 clock framework support. The main clock parent is automatically detected, but most of the clocks are not used by any driver or subsystem at this point. More work is needed for support of multi media hardware such as FSI and/or LCDC/MIPI-DSI. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-12-03 07:22:31 +00:00
extern struct clk sh73a0_extal1_clk;
extern struct clk sh73a0_extal2_clk;
sh: clkfwk: clock-sh73a0: all div6_clks use SH_CLK_DIV6_EXT() Current div6 clocks can specify their current parent clocks from its register value if it is registered by sh_clk_div6_reparent_register(). This patch modifies all div6 clocks into SH_CLK_DIV6_EXT(). Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-12-05 22:29:15 -08:00
extern struct clk sh73a0_extcki_clk;
extern struct clk sh73a0_extalr_clk;
ARM: mach-shmobile: Initial AG5 and AG5EVM support This patch adds initial support for Renesas SH-Mobile AG5. At this point the AG5 CPU support is limited to the ARM core, SCIF serial and a CMT timer together with L2 cache and the GIC. The AG5EVM board also supports Ethernet. Future patches will add support for GPIO, INTCS, CPGA and platform data / driver updates for devices such as IIC, LCDC, FSI, KEYSC, CEU and SDHI among others. The code in entry-macro.S will be cleaned up when the ARM IRQ demux code improvements have been merged. Depends on the AG5EVM mach-type recently registered but not yet present in arch/arm/tools/mach-types. As the AG5EVM board comes with 512MiB memory it is recommended to turn on HIGHMEM. Many thanks to Yoshii-san for initial bring up. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-11-17 10:59:31 +00:00
ARM: mach-shmobile: R-Mobile A1 support. This adds preliminary support for the R8A7740 (R-Mobile A1) CPU Timer, serial, gic, clock are supported at this point. This patch is based on v0.1 manual Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-11-10 18:45:52 -08:00
extern void r8a7740_init_irq(void);
ARM: mach-shmobile: r8a7740 map_io and init_early update Update the r8a7740 SoC and the Bonito board to make use of the functions r8a7740_map_io() and r8a7740_add_early_devices(). Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-02-29 21:37:35 +09:00
extern void r8a7740_map_io(void);
ARM: mach-shmobile: R-Mobile A1 support. This adds preliminary support for the R8A7740 (R-Mobile A1) CPU Timer, serial, gic, clock are supported at this point. This patch is based on v0.1 manual Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-11-10 18:45:52 -08:00
extern void r8a7740_add_early_devices(void);
extern void r8a7740_add_standard_devices(void);
extern void r8a7740_clock_init(u8 md_ck);
extern void r8a7740_pinmux_init(void);
ARM: shmobile: r8a7740: Add CPU sleep suspend Add the lighest possible sleep mode on Cortex-A9 cores: CPU sleep. It is entered by a simple dsb and wfi instruction via cpu_do_idle(). As just clocks are stopped there is no need to save or restore any state of the system. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> [ horms@verge.net.au: Added missing includes ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2012-12-05 12:13:07 +00:00
extern void r8a7740_pm_init(void);
ARM: mach-shmobile: R-Mobile A1 support. This adds preliminary support for the R8A7740 (R-Mobile A1) CPU Timer, serial, gic, clock are supported at this point. This patch is based on v0.1 manual Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-11-10 18:45:52 -08:00
ARM: mach-shmobile: r8a7779 and Marzen base support V2 Initial support for the r8a7779 SoC and the Marzen board (V2). Only SCIF ports and the TMU are supported at this point. To keep things simple only entity-mapped virt-to-phys mappings are supported. This forces drivers and other SoC glue code to make use of ioremap(). We cannot support early serial console due to virtual address space collisions with the ARM kernel. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-12-14 01:36:12 +09:00
extern void r8a7779_init_irq(void);
ARM: mach-shmobile: r8a7779 map_io and init_early update Update the r8a7779 SoC and the Marzen board to make use of the functions r8a7779_map_io() and r8a7779_add_early_devices(). Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-02-29 21:37:43 +09:00
extern void r8a7779_map_io(void);
ARM: delete struct sys_timer Now that the only field in struct sys_timer is .init, delete the struct, and replace the machine descriptor .timer field with the initialization function itself. This will enable moving timer drivers into drivers/clocksource without having to place a public prototype of each struct sys_timer object into include/linux; the intent is to create a single of_clocksource_init() function that determines which timer driver to initialize by scanning the device dtree, much like the proposed irqchip_init() at: http://www.spinics.net/lists/arm-kernel/msg203686.html Includes mach-omap2 fixes from Igor Grinberg. Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
2012-11-08 12:40:59 -07:00
extern void r8a7779_earlytimer_init(void);
ARM: mach-shmobile: r8a7779 and Marzen base support V2 Initial support for the r8a7779 SoC and the Marzen board (V2). Only SCIF ports and the TMU are supported at this point. To keep things simple only entity-mapped virt-to-phys mappings are supported. This forces drivers and other SoC glue code to make use of ioremap(). We cannot support early serial console due to virtual address space collisions with the ARM kernel. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-12-14 01:36:12 +09:00
extern void r8a7779_add_early_devices(void);
extern void r8a7779_add_standard_devices(void);
extern void r8a7779_clock_init(void);
ARM: mach-shmobile: r8a7779 PFC GPIO-only support V2 Add GPIO-only r8a7779 PFC support V2. Only regular GPIOs are supported at this time. GPIO_FN are not supported because they require variable bit width support in be the shared pfc code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-12-14 01:36:22 +09:00
extern void r8a7779_pinmux_init(void);
ARM: mach-shmobile: r8a7779 power domain support V2 Add power domain control support for the r8a7779 SoC V2. This adds support for 4 power domains for I/O Devices together with code that can be used for CPU cores as well. The only out of the ordinary experience is the need for ioremap() of SYSC registers. Because of that we need to execute some init function before setting up the domains. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2012-01-10 15:50:01 +09:00
extern void r8a7779_pm_init(void);
ARM: shmobile: r8a7740: add MERAM work-around r8a7740 chip has lasting errata on MERAM buffer, and this patch adds its work-around on setup-r8a7740.c It solved CEU/VIO6C/2D-DMAC/VCP1/VPU5F/JPU/DISP memroy access error. But MERAM driver can't control this issue, since this work-around requires access to non-MERAM register address. So, This it will be called as board specific code at this point. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Simon Horman <horms@verge.net.au> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-06-12 02:36:21 -07:00
extern void r8a7740_meram_workaround(void);
ARM: mach-shmobile: r8a7779 and Marzen base support V2 Initial support for the r8a7779 SoC and the Marzen board (V2). Only SCIF ports and the TMU are supported at this point. To keep things simple only entity-mapped virt-to-phys mappings are supported. This forces drivers and other SoC glue code to make use of ioremap(). We cannot support early serial console due to virtual address space collisions with the ARM kernel. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2011-12-14 01:36:12 +09:00
ARM / mach-shmobile: r8a7779 SMP TWD boot regression fix Fix SMP TWD boot regression on r8a7779 based platforms caused by: 4200b16 ARM: shmobile: convert to twd_local_timer_register() interface After the merge of the above commit it has been impossible to boot r8a7779 based SoCs with SMP enabled and CONFIG_HAVE_ARM_TWD=y. The kernel crashes at smp_init_cpus() timing which is before the console has been initialized, so to the user this looks like a kernel lock up without any particular error message. This patch fixes the regression on r8a7779 by moving the TWD registration code from smp_init_cpus() to sys_timer->init() time. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
2012-05-10 14:57:22 +09:00
extern void r8a7779_register_twd(void);
ARM: mach-shmobile: r8a7779 SMP support V3 This patch contains r8a7779 SMP support V3 - now including CPU hotplug offine and online support. The r8a7779 power domain code is tied together with SMP glue code which allows us to control the power domains via CPU hotplug. At this point the kernel boots with the 4 Cortex-A9 cores in SMP mode and all CPU cores except CPU0 can be hotplugged. The code in platsmp.c is quite far from pretty, but it is kept like that intentionally to avoid creating layers of code that will go away in the near future anyway. The code needs to be updated when some per-SoC handling code will be added to the ARM architecture, see the following patch for more information: "[RFC PATCH 0/3] Per SoC descriptor" Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2012-01-10 17:44:39 +09:00
ARM: shmobile: use machine specific hook for late init Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Magnus Damm <damm@opensource.se> Acked-by: "Rafael J. Wysocki" <rjw@sisk.pl>
2012-04-26 21:58:41 +08:00
#ifdef CONFIG_SUSPEND
int shmobile_suspend_init(void);
#else
static inline int shmobile_suspend_init(void) { return 0; }
#endif
#ifdef CONFIG_CPU_IDLE
int shmobile_cpuidle_init(void);
#else
static inline int shmobile_cpuidle_init(void) { return 0; }
#endif
ARM: SoC: convert shmobile SMP to SMP operations Convert shmobile SMP platforms to use struct smp_operations to provide their SMP and CPU hotplug operations. Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2011-09-08 13:15:22 +01:00
extern void shmobile_cpu_die(unsigned int cpu);
extern int shmobile_cpu_disable(unsigned int cpu);
ARM: mach-shmobile: add shmobile_cpu_disable_any() Method to disable any core to be used on platforms where CPU0 does not need special treatment. Signed-off-by: Ulrich Hecht <ulrich.hecht@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2013-01-10 11:16:43 +01:00
extern int shmobile_cpu_disable_any(unsigned int cpu);
ARM: SoC: convert shmobile SMP to SMP operations Convert shmobile SMP platforms to use struct smp_operations to provide their SMP and CPU hotplug operations. Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2011-09-08 13:15:22 +01:00
#ifdef CONFIG_HOTPLUG_CPU
extern int shmobile_cpu_is_dead(unsigned int cpu);
#else
static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
#endif
extern void shmobile_smp_init_cpus(unsigned int ncores);
ARM: shmobile: mark shmobile_init_late as __init Patch 35f2b0bd59 "ARM: shmobile: Move definition of shmobile_init_late() to header" moved the definition of the shmobile_init_late function, but dropped the __init annotation, which is now causing warnings because the function calls shmobile_suspend_init, which is also marked init. Without this patch, building kota2_defconfig results in: WARNING: vmlinux.o(.text+0xb7c8): Section mismatch in reference from the function shmobile_init_late() to the function .init.text:shmobile_suspend_init() The function shmobile_init_late() references the function __init shmobile_suspend_init(). This is often because shmobile_init_late lacks a __init annotation or the annotation of shmobile_suspend_init is wrong. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Rafael J. Wysocki <rjw@sisk.pl> Cc: Magnus Damm <damm@opensource.se> Cc: Simon Horman <horms@verge.net.au>
2012-09-23 22:36:35 +00:00
static inline void __init shmobile_init_late(void)
ARM: shmobile: Move definition of shmobile_init_late() to header The role of the only function in the common.c file in arch/arm/mach-shmobile, shmobile_init_late(), is to call two initializers whose definitions depend on kernel configuration options. Those initializers may very well be called from a static inline function in arm/mach-shmobile/include/mach/common.h, though, in which makes the code a bit easier to read. Moreover, the common.c may be dropped entirely then. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Magnus Damm <damm@opensource.se>
2012-08-15 20:57:27 +02:00
{
shmobile_suspend_init();
shmobile_cpuidle_init();
}
ARM: mach-shmobile: SH-Mobile G3 support. This adds preliminary support for the SH-Mobile G-series. The SH-Mobile G-series is a series of ARM/SH multi-core CPUs that aside from the ARM MPU are primarily composed of existing SH IP blocks. This includes initial support for the SH7367 (SH-Mobile G3) CPU and the G3EVM reference board. Only timer, serial console, and NOR flash are supported at this point. Patches for the interrupt controller, pinmux support, clock framework and runtime pm will be submitted as feature patches on top of this. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-02-05 11:14:49 +00:00
#endif /* __ARCH_MACH_COMMON_H */
Reference in a new issue Copy permalink