2005-04-16 15:20:36 -07:00
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/*
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* Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*/
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#ifndef _ASM_GT64120_H
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#define _ASM_GT64120_H
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#include <asm/addrspace.h>
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#include <asm/byteorder.h>
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#define MSK(n) ((1 << (n)) - 1)
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/*
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* Register offset addresses
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*/
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/* CPU Configuration. */
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#define GT_CPU_OFS 0x000
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#define GT_MULTI_OFS 0x120
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/* CPU Address Decode. */
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#define GT_SCS10LD_OFS 0x008
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#define GT_SCS10HD_OFS 0x010
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#define GT_SCS32LD_OFS 0x018
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#define GT_SCS32HD_OFS 0x020
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#define GT_CS20LD_OFS 0x028
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#define GT_CS20HD_OFS 0x030
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#define GT_CS3BOOTLD_OFS 0x038
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#define GT_CS3BOOTHD_OFS 0x040
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#define GT_PCI0IOLD_OFS 0x048
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#define GT_PCI0IOHD_OFS 0x050
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#define GT_PCI0M0LD_OFS 0x058
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#define GT_PCI0M0HD_OFS 0x060
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#define GT_ISD_OFS 0x068
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#define GT_PCI0M1LD_OFS 0x080
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#define GT_PCI0M1HD_OFS 0x088
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#define GT_PCI1IOLD_OFS 0x090
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#define GT_PCI1IOHD_OFS 0x098
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#define GT_PCI1M0LD_OFS 0x0a0
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#define GT_PCI1M0HD_OFS 0x0a8
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#define GT_PCI1M1LD_OFS 0x0b0
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#define GT_PCI1M1HD_OFS 0x0b8
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#define GT_PCI1M1LD_OFS 0x0b0
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#define GT_PCI1M1HD_OFS 0x0b8
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#define GT_SCS10AR_OFS 0x0d0
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#define GT_SCS32AR_OFS 0x0d8
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#define GT_CS20R_OFS 0x0e0
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#define GT_CS3BOOTR_OFS 0x0e8
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#define GT_PCI0IOREMAP_OFS 0x0f0
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#define GT_PCI0M0REMAP_OFS 0x0f8
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#define GT_PCI0M1REMAP_OFS 0x100
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#define GT_PCI1IOREMAP_OFS 0x108
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#define GT_PCI1M0REMAP_OFS 0x110
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#define GT_PCI1M1REMAP_OFS 0x118
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/* CPU Error Report. */
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#define GT_CPUERR_ADDRLO_OFS 0x070
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#define GT_CPUERR_ADDRHI_OFS 0x078
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#define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */
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#define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */
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#define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */
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/* CPU Sync Barrier. */
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#define GT_PCI0SYNC_OFS 0x0c0
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#define GT_PCI1SYNC_OFS 0x0c8
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/* SDRAM and Device Address Decode. */
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#define GT_SCS0LD_OFS 0x400
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#define GT_SCS0HD_OFS 0x404
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#define GT_SCS1LD_OFS 0x408
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#define GT_SCS1HD_OFS 0x40c
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#define GT_SCS2LD_OFS 0x410
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#define GT_SCS2HD_OFS 0x414
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#define GT_SCS3LD_OFS 0x418
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#define GT_SCS3HD_OFS 0x41c
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#define GT_CS0LD_OFS 0x420
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#define GT_CS0HD_OFS 0x424
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#define GT_CS1LD_OFS 0x428
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#define GT_CS1HD_OFS 0x42c
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#define GT_CS2LD_OFS 0x430
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#define GT_CS2HD_OFS 0x434
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#define GT_CS3LD_OFS 0x438
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#define GT_CS3HD_OFS 0x43c
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#define GT_BOOTLD_OFS 0x440
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#define GT_BOOTHD_OFS 0x444
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#define GT_ADERR_OFS 0x470
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/* SDRAM Configuration. */
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#define GT_SDRAM_CFG_OFS 0x448
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#define GT_SDRAM_OPMODE_OFS 0x474
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#define GT_SDRAM_BM_OFS 0x478
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#define GT_SDRAM_ADDRDECODE_OFS 0x47c
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/* SDRAM Parameters. */
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#define GT_SDRAM_B0_OFS 0x44c
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#define GT_SDRAM_B1_OFS 0x450
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#define GT_SDRAM_B2_OFS 0x454
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#define GT_SDRAM_B3_OFS 0x458
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/* Device Parameters. */
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#define GT_DEV_B0_OFS 0x45c
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#define GT_DEV_B1_OFS 0x460
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#define GT_DEV_B2_OFS 0x464
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#define GT_DEV_B3_OFS 0x468
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#define GT_DEV_BOOT_OFS 0x46c
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/* ECC. */
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#define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */
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#define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */
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#define GT_ECC_MEM 0x488 /* GT-64120A only */
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#define GT_ECC_CALC 0x48c /* GT-64120A only */
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#define GT_ECC_ERRADDR 0x490 /* GT-64120A only */
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/* DMA Record. */
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#define GT_DMA0_CNT_OFS 0x800
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#define GT_DMA1_CNT_OFS 0x804
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#define GT_DMA2_CNT_OFS 0x808
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#define GT_DMA3_CNT_OFS 0x80c
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#define GT_DMA0_SA_OFS 0x810
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#define GT_DMA1_SA_OFS 0x814
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#define GT_DMA2_SA_OFS 0x818
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#define GT_DMA3_SA_OFS 0x81c
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#define GT_DMA0_DA_OFS 0x820
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#define GT_DMA1_DA_OFS 0x824
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#define GT_DMA2_DA_OFS 0x828
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#define GT_DMA3_DA_OFS 0x82c
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#define GT_DMA0_NEXT_OFS 0x830
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#define GT_DMA1_NEXT_OFS 0x834
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#define GT_DMA2_NEXT_OFS 0x838
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#define GT_DMA3_NEXT_OFS 0x83c
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#define GT_DMA0_CUR_OFS 0x870
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#define GT_DMA1_CUR_OFS 0x874
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#define GT_DMA2_CUR_OFS 0x878
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#define GT_DMA3_CUR_OFS 0x87c
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/* DMA Channel Control. */
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#define GT_DMA0_CTRL_OFS 0x840
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#define GT_DMA1_CTRL_OFS 0x844
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#define GT_DMA2_CTRL_OFS 0x848
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#define GT_DMA3_CTRL_OFS 0x84c
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/* DMA Arbiter. */
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#define GT_DMA_ARB_OFS 0x860
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/* Timer/Counter. */
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#define GT_TC0_OFS 0x850
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#define GT_TC1_OFS 0x854
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#define GT_TC2_OFS 0x858
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#define GT_TC3_OFS 0x85c
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#define GT_TC_CONTROL_OFS 0x864
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/* PCI Internal. */
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#define GT_PCI0_CMD_OFS 0xc00
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#define GT_PCI0_TOR_OFS 0xc04
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#define GT_PCI0_BS_SCS10_OFS 0xc08
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#define GT_PCI0_BS_SCS32_OFS 0xc0c
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#define GT_PCI0_BS_CS20_OFS 0xc10
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#define GT_PCI0_BS_CS3BT_OFS 0xc14
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#define GT_PCI1_IACK_OFS 0xc30
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#define GT_PCI0_IACK_OFS 0xc34
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#define GT_PCI0_BARE_OFS 0xc3c
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#define GT_PCI0_PREFMBR_OFS 0xc40
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#define GT_PCI0_SCS10_BAR_OFS 0xc48
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#define GT_PCI0_SCS32_BAR_OFS 0xc4c
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#define GT_PCI0_CS20_BAR_OFS 0xc50
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#define GT_PCI0_CS3BT_BAR_OFS 0xc54
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#define GT_PCI0_SSCS10_BAR_OFS 0xc58
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#define GT_PCI0_SSCS32_BAR_OFS 0xc5c
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#define GT_PCI0_SCS3BT_BAR_OFS 0xc64
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#define GT_PCI1_CMD_OFS 0xc80
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#define GT_PCI1_TOR_OFS 0xc84
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#define GT_PCI1_BS_SCS10_OFS 0xc88
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#define GT_PCI1_BS_SCS32_OFS 0xc8c
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#define GT_PCI1_BS_CS20_OFS 0xc90
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#define GT_PCI1_BS_CS3BT_OFS 0xc94
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#define GT_PCI1_BARE_OFS 0xcbc
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#define GT_PCI1_PREFMBR_OFS 0xcc0
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#define GT_PCI1_SCS10_BAR_OFS 0xcc8
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#define GT_PCI1_SCS32_BAR_OFS 0xccc
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#define GT_PCI1_CS20_BAR_OFS 0xcd0
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#define GT_PCI1_CS3BT_BAR_OFS 0xcd4
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#define GT_PCI1_SSCS10_BAR_OFS 0xcd8
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#define GT_PCI1_SSCS32_BAR_OFS 0xcdc
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#define GT_PCI1_SCS3BT_BAR_OFS 0xce4
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#define GT_PCI1_CFGADDR_OFS 0xcf0
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#define GT_PCI1_CFGDATA_OFS 0xcf4
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#define GT_PCI0_CFGADDR_OFS 0xcf8
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#define GT_PCI0_CFGDATA_OFS 0xcfc
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/* Interrupts. */
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#define GT_INTRCAUSE_OFS 0xc18
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#define GT_INTRMASK_OFS 0xc1c
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#define GT_PCI0_ICMASK_OFS 0xc24
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#define GT_PCI0_SERR0MASK_OFS 0xc28
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#define GT_CPU_INTSEL_OFS 0xc70
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#define GT_PCI0_INTSEL_OFS 0xc74
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#define GT_HINTRCAUSE_OFS 0xc98
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#define GT_HINTRMASK_OFS 0xc9c
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#define GT_PCI0_HICMASK_OFS 0xca4
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#define GT_PCI1_SERR1MASK_OFS 0xca8
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/*
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* I2O Support Registers
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*/
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#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
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#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
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#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
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#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
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#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
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#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
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#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
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#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
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#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
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#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
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#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
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#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
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#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
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#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
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#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
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#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
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#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
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#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
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#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
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#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
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#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
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#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
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#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
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#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
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#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
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#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
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#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
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#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
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#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
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#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
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#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
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#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
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#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
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#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
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#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
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#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
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#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
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#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
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#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
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#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
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#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
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#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
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#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
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#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
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/*
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* Register encodings
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*/
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#define GT_CPU_ENDIAN_SHF 12
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#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
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#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
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#define GT_CPU_WR_SHF 16
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#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
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#define GT_CPU_WR_BIT GT_CPU_WR_MSK
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#define GT_CPU_WR_DXDXDXDX 0
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#define GT_CPU_WR_DDDD 1
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#define GT_PCI_DCRM_SHF 21
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#define GT_PCI_LD_SHF 0
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#define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF)
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#define GT_PCI_HD_SHF 0
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#define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF)
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#define GT_PCI_REMAP_SHF 0
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#define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF)
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#define GT_CFGADDR_CFGEN_SHF 31
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#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
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#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
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#define GT_CFGADDR_BUSNUM_SHF 16
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#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
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#define GT_CFGADDR_DEVNUM_SHF 11
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#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
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#define GT_CFGADDR_FUNCNUM_SHF 8
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#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
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#define GT_CFGADDR_REGNUM_SHF 2
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#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
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#define GT_SDRAM_BM_ORDER_SHF 2
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#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
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#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
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#define GT_SDRAM_BM_ORDER_SUB 1
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#define GT_SDRAM_BM_ORDER_LIN 0
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#define GT_SDRAM_BM_RSVD_ALL1 0xffb
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#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
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#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
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#define GT_SDRAM_ADDRDECODE_ADDR_0 0
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#define GT_SDRAM_ADDRDECODE_ADDR_1 1
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#define GT_SDRAM_ADDRDECODE_ADDR_2 2
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#define GT_SDRAM_ADDRDECODE_ADDR_3 3
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#define GT_SDRAM_ADDRDECODE_ADDR_4 4
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#define GT_SDRAM_ADDRDECODE_ADDR_5 5
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#define GT_SDRAM_ADDRDECODE_ADDR_6 6
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#define GT_SDRAM_ADDRDECODE_ADDR_7 7
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#define GT_SDRAM_B0_CASLAT_SHF 0
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#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
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#define GT_SDRAM_B0_CASLAT_2 1
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#define GT_SDRAM_B0_CASLAT_3 2
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#define GT_SDRAM_B0_FTDIS_SHF 2
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#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
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#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
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#define GT_SDRAM_B0_SRASPRCHG_SHF 3
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#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
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#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
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#define GT_SDRAM_B0_SRASPRCHG_2 0
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#define GT_SDRAM_B0_SRASPRCHG_3 1
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#define GT_SDRAM_B0_B0COMPAB_SHF 4
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#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
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#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
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#define GT_SDRAM_B0_64BITINT_SHF 5
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#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
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#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
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#define GT_SDRAM_B0_64BITINT_2 0
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#define GT_SDRAM_B0_64BITINT_4 1
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#define GT_SDRAM_B0_BW_SHF 6
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#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
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#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
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#define GT_SDRAM_B0_BW_32 0
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#define GT_SDRAM_B0_BW_64 1
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#define GT_SDRAM_B0_BLODD_SHF 7
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|
|
#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
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#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
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#define GT_SDRAM_B0_PAR_SHF 8
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#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
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#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
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#define GT_SDRAM_B0_BYPASS_SHF 9
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|
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#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
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|
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#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
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#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
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#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
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#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
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#define GT_SDRAM_B0_SRAS2SCAS_2 0
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|
|
#define GT_SDRAM_B0_SRAS2SCAS_3 1
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|
|
#define GT_SDRAM_B0_SIZE_SHF 11
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|
#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
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|
|
#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
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|
|
#define GT_SDRAM_B0_SIZE_16M 0
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|
|
#define GT_SDRAM_B0_SIZE_64M 1
|
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|
#define GT_SDRAM_B0_EXTPAR_SHF 12
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|
|
#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
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|
|
#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
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#define GT_SDRAM_B0_BLEN_SHF 13
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|
|
#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
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|
|
#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
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|
|
#define GT_SDRAM_B0_BLEN_8 0
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|
|
#define GT_SDRAM_B0_BLEN_4 1
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|
|
#define GT_SDRAM_CFG_REFINT_SHF 0
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|
|
#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
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|
|
#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
|
|
|
|
|
#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
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|
|
#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
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|
|
#define GT_SDRAM_CFG_RMW_SHF 15
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|
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|
|
#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
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|
|
#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
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|
#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
|
|
|
|
|
#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
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|
|
#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
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|
|
#define GT_SDRAM_CFG_DUPCNTL_SHF 19
|
|
|
|
|
#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
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|
|
#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
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|
|
#define GT_SDRAM_CFG_DUPBA_SHF 20
|
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|
|
#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
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|
|
#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
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#define GT_SDRAM_CFG_DUPEOT0_SHF 21
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|
|
#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
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|
|
#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
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|
|
#define GT_SDRAM_CFG_DUPEOT1_SHF 22
|
|
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|
|
#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
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|
|
#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
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|
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#define GT_SDRAM_OPMODE_OP_SHF 0
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|
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|
|
#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
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|
|
#define GT_SDRAM_OPMODE_OP_NORMAL 0
|
|
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|
|
#define GT_SDRAM_OPMODE_OP_NOP 1
|
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|
|
|
#define GT_SDRAM_OPMODE_OP_PRCHG 2
|
|
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|
|
#define GT_SDRAM_OPMODE_OP_MODE 3
|
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|
|
#define GT_SDRAM_OPMODE_OP_CBR 4
|
|
|
|
|
|
2006-10-14 00:25:04 +09:00
|
|
|
#define GT_TC_CONTROL_ENTC0_SHF 0
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|
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|
|
#define GT_TC_CONTROL_ENTC0_MSK (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
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|
|
#define GT_TC_CONTROL_ENTC0_BIT GT_TC_CONTROL_ENTC0_MSK
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|
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#define GT_TC_CONTROL_SELTC0_SHF 1
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|
|
#define GT_TC_CONTROL_SELTC0_MSK (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
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#define GT_TC_CONTROL_SELTC0_BIT GT_TC_CONTROL_SELTC0_MSK
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|
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|
|
|
2005-04-16 15:20:36 -07:00
|
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|
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|
|
#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
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|
|
|
|
#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
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|
|
#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
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#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
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|
|
#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
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|
|
#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
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#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
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|
|
#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
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|
|
#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
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|
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#define GT_PCI0_BARE_INTIODIS_SHF 3
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|
|
#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
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|
|
#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
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#define GT_PCI0_BARE_INTMEMDIS_SHF 4
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|
|
#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
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|
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#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
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#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
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|
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#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
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|
|
#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
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#define GT_PCI0_BARE_CS20DIS_SHF 6
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|
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#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
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|
|
#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
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#define GT_PCI0_BARE_SCS32DIS_SHF 7
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|
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#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
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#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
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#define GT_PCI0_BARE_SCS10DIS_SHF 8
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#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
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#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
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#define GT_INTRCAUSE_MASABORT0_SHF 18
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|
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#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
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#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
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#define GT_INTRCAUSE_TARABORT0_SHF 19
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|
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#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
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|
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#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
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#define GT_PCI0_CFGADDR_REGNUM_SHF 2
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|
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#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
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|
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#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
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|
|
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
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#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
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#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
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#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
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#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
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#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
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#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
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#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
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#define GT_PCI0_CMD_MBYTESWAP_SHF 0
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#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
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#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
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#define GT_PCI0_CMD_MWORDSWAP_SHF 10
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#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
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#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
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#define GT_PCI0_CMD_SBYTESWAP_SHF 16
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#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
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#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
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#define GT_PCI0_CMD_SWORDSWAP_SHF 11
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#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
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#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
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2006-10-14 00:25:04 +09:00
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#define GT_INTR_T0EXP_SHF 8
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#define GT_INTR_T0EXP_MSK (MSK(1) << GT_INTR_T0EXP_SHF)
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#define GT_INTR_T0EXP_BIT GT_INTR_T0EXP_MSK
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#define GT_INTR_RETRYCTR0_SHF 20
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#define GT_INTR_RETRYCTR0_MSK (MSK(1) << GT_INTR_RETRYCTR0_SHF)
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#define GT_INTR_RETRYCTR0_BIT GT_INTR_RETRYCTR0_MSK
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2005-04-16 15:20:36 -07:00
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/*
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* Misc
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*/
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#define GT_DEF_PCI0_IO_BASE 0x10000000UL
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#define GT_DEF_PCI0_IO_SIZE 0x02000000UL
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#define GT_DEF_PCI0_MEM0_BASE 0x12000000UL
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#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL
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#define GT_DEF_BASE 0x14000000UL
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#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
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#define GT_LATTIM_MIN 6 /* Minimum lat */
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/*
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* The gt64120_dep.h file must define the following macros
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*
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* GT_READ(ofs, data_pointer)
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* GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit
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*
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* TIMER - gt64120 timer irq, temporary solution until
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* full gt64120 cascade interrupt support is in place
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*/
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#include <mach-gt64120.h>
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/*
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* Because of an error/peculiarity in the Galileo chip, we need to swap the
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* bytes when running bigendian. We also provide non-swapping versions.
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*/
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#define __GT_READ(ofs) \
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(*(volatile u32 *)(GT64120_BASE+(ofs)))
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#define __GT_WRITE(ofs, data) \
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do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
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#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
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#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
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2007-10-22 19:43:15 +09:00
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extern void gt641xx_set_base_clock(unsigned int clock);
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extern int gt641xx_timer0_state(void);
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2005-04-16 15:20:36 -07:00
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#endif /* _ASM_GT64120_H */
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