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										 |  |  | /*
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							|  |  |  |  * Format of an instruction in memory. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This file is subject to the terms and conditions of the GNU General Public | 
					
						
							|  |  |  |  * License.  See the file "COPYING" in the main directory of this archive | 
					
						
							|  |  |  |  * for more details. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Copyright (C) 1996, 2000 by Ralf Baechle | 
					
						
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											2006-05-15 18:27:03 +01:00
										 |  |  |  * Copyright (C) 2006 by Thiemo Seufer | 
					
						
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										 |  |  |  */ | 
					
						
							|  |  |  | #ifndef _ASM_INST_H
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							|  |  |  | #define _ASM_INST_H
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										 |  |  | #include <uapi/asm/inst.h>
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										 |  |  | 
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							|  |  |  | /* HACHACHAHCAHC ...  */ | 
					
						
							|  |  |  | 
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							|  |  |  | /* In case some other massaging is needed, keep MIPSInst as wrapper */ | 
					
						
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							|  |  |  | #define MIPSInst(x) x
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							|  |  |  | #define I_OPCODE_SFT	26
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							|  |  |  | #define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
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							|  |  |  | #define I_JTARGET_SFT	0
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							|  |  |  | #define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
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							|  |  |  | #define I_RS_SFT	21
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							|  |  |  | #define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
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							|  |  |  | #define I_RT_SFT	16
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							|  |  |  | #define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
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							|  |  |  | #define I_IMM_SFT	0
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							|  |  |  | #define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
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							|  |  |  | #define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
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							|  |  |  | #define I_CACHEOP_SFT	18
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							|  |  |  | #define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
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							|  |  |  | #define I_CACHESEL_SFT	16
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							|  |  |  | #define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
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							|  |  |  | #define I_RD_SFT	11
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							|  |  |  | #define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
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							|  |  |  | #define I_RE_SFT	6
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							|  |  |  | #define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
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							|  |  |  | #define I_FUNC_SFT	0
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							|  |  |  | #define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
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							|  |  |  | #define I_FFMT_SFT	21
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							|  |  |  | #define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
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							|  |  |  | #define I_FT_SFT	16
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							|  |  |  | #define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
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							|  |  |  | #define I_FS_SFT	11
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							|  |  |  | #define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
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							|  |  |  | #define I_FD_SFT	6
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							|  |  |  | #define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
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							|  |  |  | #define I_FR_SFT	21
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							|  |  |  | #define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
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							|  |  |  | #define I_FMA_FUNC_SFT	2
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							|  |  |  | #define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
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							|  |  |  | #define I_FMA_FFMT_SFT	0
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							|  |  |  | #define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
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							|  |  |  | typedef unsigned int mips_instruction; | 
					
						
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										 |  |  | /* microMIPS instruction decode structure. Do NOT export!!! */ | 
					
						
							|  |  |  | struct mm_decoded_insn { | 
					
						
							|  |  |  | 	mips_instruction insn; | 
					
						
							|  |  |  | 	mips_instruction next_insn; | 
					
						
							|  |  |  | 	int pc_inc; | 
					
						
							|  |  |  | 	int next_pc_inc; | 
					
						
							|  |  |  | 	int micro_mips_mode; | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | /* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */ | 
					
						
							|  |  |  | extern const int reg16to32[]; | 
					
						
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										 |  |  | #endif /* _ASM_INST_H */
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