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										 |  |  | /* | 
					
						
							|  |  |  |  *  Copyright (C) 2003-2005 SAN People | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Debugging macro include header | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This program is free software; you can redistribute it and/or modify
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							|  |  |  |  * it under the terms of the GNU General Public License version 2 as | 
					
						
							|  |  |  |  * published by the Free Software Foundation. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  | */ | 
					
						
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										 |  |  | #if defined(CONFIG_AT91_DEBUG_LL_DBGU0) | 
					
						
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										 |  |  | #define AT91_DBGU 0xfffff200 /* AT91_BASE_DBGU0 */ | 
					
						
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										 |  |  | #elif defined(CONFIG_AT91_DEBUG_LL_DBGU1) | 
					
						
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										 |  |  | #define AT91_DBGU 0xffffee00 /* AT91_BASE_DBGU1 */ | 
					
						
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										 |  |  | #else | 
					
						
							|  |  |  | /* On sama5d4, use USART3 as low level serial console */ | 
					
						
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										 |  |  | #define AT91_DBGU 0xfc00c000 /* SAMA5D4_BASE_USART3 */ | 
					
						
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										 |  |  | #endif | 
					
						
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										 |  |  | #ifdef CONFIG_MMU | 
					
						
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										 |  |  | #define AT91_IO_P2V(x) ((x) - 0x01000000) | 
					
						
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										 |  |  | #else | 
					
						
							|  |  |  | #define AT91_IO_P2V(x) (x) | 
					
						
							|  |  |  | #endif | 
					
						
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							|  |  |  | #define AT91_DBGU_SR		(0x14)	/* Status Register */ | 
					
						
							|  |  |  | #define AT91_DBGU_THR		(0x1c)	/* Transmitter Holding Register */ | 
					
						
							|  |  |  | #define AT91_DBGU_TXRDY		(1 << 1)	/* Transmitter Ready */ | 
					
						
							|  |  |  | #define AT91_DBGU_TXEMPTY	(1 << 9)	/* Transmitter Empty */ | 
					
						
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										 |  |  | 	.macro	addruart, rp, rv, tmp | 
					
						
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										 |  |  | 	ldr	\rp, =AT91_DBGU				@ System peripherals (phys address)
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							|  |  |  | 	ldr	\rv, =AT91_IO_P2V(AT91_DBGU)		@ System peripherals (virt address)
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										 |  |  | 	.endm | 
					
						
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							|  |  |  | 	.macro	senduart,rd,rx | 
					
						
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										 |  |  | 	strb	\rd, [\rx, #(AT91_DBGU_THR)]		@ Write to Transmitter Holding Register
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										 |  |  | 	.endm | 
					
						
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							|  |  |  | 	.macro	waituart,rd,rx | 
					
						
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										 |  |  | 1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR)]		@ Read Status Register
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							|  |  |  | 	tst	\rd, #AT91_DBGU_TXRDY			@ DBGU_TXRDY = 1 when ready to transmit
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										 |  |  | 	beq	1001b | 
					
						
							|  |  |  | 	.endm | 
					
						
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							|  |  |  | 	.macro	busyuart,rd,rx | 
					
						
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										 |  |  | 1001:	ldr	\rd, [\rx, #(AT91_DBGU_SR)]		@ Read Status Register
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							|  |  |  | 	tst	\rd, #AT91_DBGU_TXEMPTY			@ DBGU_TXEMPTY = 1 when transmission complete
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										 |  |  | 	beq	1001b | 
					
						
							|  |  |  | 	.endm | 
					
						
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