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										 |  |  | /*
 | 
					
						
							|  |  |  |  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This program is free software; you can redistribute it and/or modify | 
					
						
							|  |  |  |  * it under the terms of the GNU General Public License version 2 as | 
					
						
							|  |  |  |  * published by the Free Software Foundation. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #include <linux/seq_file.h>
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							|  |  |  | #include <linux/fs.h>
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							|  |  |  | #include <linux/delay.h>
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							|  |  |  | #include <linux/root_dev.h>
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							|  |  |  | #include <linux/console.h>
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							|  |  |  | #include <linux/module.h>
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							|  |  |  | #include <linux/cpu.h>
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										 |  |  | #include <linux/clk-provider.h>
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										 |  |  | #include <linux/of_fdt.h>
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										 |  |  | #include <linux/of_platform.h>
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										 |  |  | #include <linux/cache.h>
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										 |  |  | #include <asm/sections.h>
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										 |  |  | #include <asm/arcregs.h>
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							|  |  |  | #include <asm/tlb.h>
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							|  |  |  | #include <asm/setup.h>
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							|  |  |  | #include <asm/page.h>
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							|  |  |  | #include <asm/irq.h>
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										 |  |  | #include <asm/unwind.h>
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										 |  |  | #include <asm/clk.h>
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										 |  |  | #include <asm/mach_desc.h>
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										 |  |  | #include <asm/smp.h>
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										 |  |  | 
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							|  |  |  | #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
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							|  |  |  | 
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										 |  |  | unsigned int intr_to_DE_cnt; | 
					
						
							|  |  |  | 
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										 |  |  | /* Part of U-boot ABI: see head.S */ | 
					
						
							|  |  |  | int __initdata uboot_tag; | 
					
						
							|  |  |  | char __initdata *uboot_arg; | 
					
						
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										 |  |  | const struct machine_desc *machine_desc; | 
					
						
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										 |  |  | 
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							|  |  |  | struct task_struct *_current_task[NR_CPUS];	/* For stack switching */ | 
					
						
							|  |  |  | 
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							|  |  |  | struct cpuinfo_arc cpuinfo_arc700[NR_CPUS]; | 
					
						
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										 |  |  | static void read_arc_build_cfg_regs(void) | 
					
						
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										 |  |  | { | 
					
						
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										 |  |  | 	struct bcr_perip uncached_space; | 
					
						
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										 |  |  | 	struct bcr_generic bcr; | 
					
						
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										 |  |  | 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; | 
					
						
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										 |  |  | 	unsigned long perip_space; | 
					
						
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										 |  |  | 	FIX_PTR(cpu); | 
					
						
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							|  |  |  | 	READ_BCR(AUX_IDENTITY, cpu->core); | 
					
						
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										 |  |  | 	READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa); | 
					
						
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										 |  |  | 
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										 |  |  | 	READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers); | 
					
						
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										 |  |  | 	cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE); | 
					
						
							|  |  |  | 
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							|  |  |  | 	READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space); | 
					
						
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										 |  |  |         if (uncached_space.ver < 3) | 
					
						
							|  |  |  | 		perip_space = uncached_space.start << 24; | 
					
						
							|  |  |  | 	else | 
					
						
							|  |  |  | 		perip_space = read_aux_reg(AUX_NON_VOL) & 0xF0000000; | 
					
						
							|  |  |  | 
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							|  |  |  | 	BUG_ON(perip_space != ARC_UNCACHED_ADDR_SPACE); | 
					
						
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										 |  |  | 
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										 |  |  | 	READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy); | 
					
						
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										 |  |  | 	cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */ | 
					
						
							|  |  |  | 	cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */ | 
					
						
							|  |  |  | 	cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0;        /* 1,3 */ | 
					
						
							|  |  |  | 	cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0; | 
					
						
							|  |  |  | 	cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */ | 
					
						
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										 |  |  | 
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										 |  |  | 	/* Note that we read the CCM BCRs independent of kernel config
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							|  |  |  | 	 * This is to catch the cases where user doesn't know that | 
					
						
							|  |  |  | 	 * CCMs are present in hardware build | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	{ | 
					
						
							|  |  |  | 		struct bcr_iccm iccm; | 
					
						
							|  |  |  | 		struct bcr_dccm dccm; | 
					
						
							|  |  |  | 		struct bcr_dccm_base dccm_base; | 
					
						
							|  |  |  | 		unsigned int bcr_32bit_val; | 
					
						
							|  |  |  | 
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							|  |  |  | 		bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR); | 
					
						
							|  |  |  | 		if (bcr_32bit_val) { | 
					
						
							|  |  |  | 			iccm = *((struct bcr_iccm *)&bcr_32bit_val); | 
					
						
							|  |  |  | 			cpu->iccm.base_addr = iccm.base << 16; | 
					
						
							|  |  |  | 			cpu->iccm.sz = 0x2000 << (iccm.sz - 1); | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 
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							|  |  |  | 		bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR); | 
					
						
							|  |  |  | 		if (bcr_32bit_val) { | 
					
						
							|  |  |  | 			dccm = *((struct bcr_dccm *)&bcr_32bit_val); | 
					
						
							|  |  |  | 			cpu->dccm.sz = 0x800 << (dccm.sz); | 
					
						
							|  |  |  | 
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							|  |  |  | 			READ_BCR(ARC_REG_DCCMBASE_BCR, dccm_base); | 
					
						
							|  |  |  | 			cpu->dccm.base_addr = dccm_base.addr << 8; | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 	} | 
					
						
							|  |  |  | 
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										 |  |  | 	READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem); | 
					
						
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										 |  |  | 	read_decode_mmu_bcr(); | 
					
						
							|  |  |  | 	read_decode_cache_bcr(); | 
					
						
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										 |  |  | 
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							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 	if (is_isa_arcompact()) { | 
					
						
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										 |  |  | 		struct bcr_fp_arcompact sp, dp; | 
					
						
							|  |  |  | 		struct bcr_bpu_arcompact bpu; | 
					
						
							|  |  |  | 
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							|  |  |  | 		READ_BCR(ARC_REG_FP_BCR, sp); | 
					
						
							|  |  |  | 		READ_BCR(ARC_REG_DPFP_BCR, dp); | 
					
						
							|  |  |  | 		cpu->extn.fpu_sp = sp.ver ? 1 : 0; | 
					
						
							|  |  |  | 		cpu->extn.fpu_dp = dp.ver ? 1 : 0; | 
					
						
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							|  |  |  | 		READ_BCR(ARC_REG_BPU_BCR, bpu); | 
					
						
							|  |  |  | 		cpu->bpu.ver = bpu.ver; | 
					
						
							|  |  |  | 		cpu->bpu.full = bpu.fam ? 1 : 0; | 
					
						
							|  |  |  | 		if (bpu.ent) { | 
					
						
							|  |  |  | 			cpu->bpu.num_cache = 256 << (bpu.ent - 1); | 
					
						
							|  |  |  | 			cpu->bpu.num_pred = 256 << (bpu.ent - 1); | 
					
						
							|  |  |  | 		} | 
					
						
							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 	} else { | 
					
						
							|  |  |  | 		struct bcr_fp_arcv2 spdp; | 
					
						
							|  |  |  | 		struct bcr_bpu_arcv2 bpu; | 
					
						
							|  |  |  | 
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							|  |  |  | 		READ_BCR(ARC_REG_FP_V2_BCR, spdp); | 
					
						
							|  |  |  | 		cpu->extn.fpu_sp = spdp.sp ? 1 : 0; | 
					
						
							|  |  |  | 		cpu->extn.fpu_dp = spdp.dp ? 1 : 0; | 
					
						
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							|  |  |  | 		READ_BCR(ARC_REG_BPU_BCR, bpu); | 
					
						
							|  |  |  | 		cpu->bpu.ver = bpu.ver; | 
					
						
							|  |  |  | 		cpu->bpu.full = bpu.ft; | 
					
						
							|  |  |  | 		cpu->bpu.num_cache = 256 << bpu.bce; | 
					
						
							|  |  |  | 		cpu->bpu.num_pred = 2048 << bpu.pte; | 
					
						
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										 |  |  | 	} | 
					
						
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							|  |  |  | 	READ_BCR(ARC_REG_AP_BCR, bcr); | 
					
						
							|  |  |  | 	cpu->extn.ap = bcr.ver ? 1 : 0; | 
					
						
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							|  |  |  | 	READ_BCR(ARC_REG_SMART_BCR, bcr); | 
					
						
							|  |  |  | 	cpu->extn.smart = bcr.ver ? 1 : 0; | 
					
						
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										 |  |  | 	READ_BCR(ARC_REG_RTT_BCR, bcr); | 
					
						
							|  |  |  | 	cpu->extn.rtt = bcr.ver ? 1 : 0; | 
					
						
							|  |  |  | 
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							|  |  |  | 	cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt; | 
					
						
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										 |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | static const struct cpuinfo_data arc_cpu_tbl[] = { | 
					
						
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										 |  |  | #ifdef CONFIG_ISA_ARCOMPACT
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										 |  |  | 	{ {0x20, "ARC 600"      }, 0x2F}, | 
					
						
							|  |  |  | 	{ {0x30, "ARC 700"      }, 0x33}, | 
					
						
							|  |  |  | 	{ {0x34, "ARC 700 R4.10"}, 0x34}, | 
					
						
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										 |  |  | 	{ {0x35, "ARC 700 R4.11"}, 0x35}, | 
					
						
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										 |  |  | #else
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							|  |  |  | 	{ {0x50, "ARC HS38 R2.0"}, 0x51}, | 
					
						
							|  |  |  | 	{ {0x52, "ARC HS38 R2.1"}, 0x52}, | 
					
						
							|  |  |  | #endif
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										 |  |  | 	{ {0x00, NULL		} } | 
					
						
							|  |  |  | }; | 
					
						
							|  |  |  | 
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										 |  |  | #define IS_AVAIL1(v, s)		((v) ? s : "")
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							|  |  |  | #define IS_USED_RUN(v)		((v) ? "" : "(not used) ")
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							|  |  |  | #define IS_USED_CFG(cfg)	IS_USED_RUN(IS_ENABLED(cfg))
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							|  |  |  | #define IS_AVAIL2(v, s, cfg)	IS_AVAIL1(v, s), IS_AVAIL1(v, IS_USED_CFG(cfg))
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										 |  |  | 
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										 |  |  | static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len) | 
					
						
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										 |  |  | { | 
					
						
							|  |  |  | 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; | 
					
						
							|  |  |  | 	struct bcr_identity *core = &cpu->core; | 
					
						
							|  |  |  | 	const struct cpuinfo_data *tbl; | 
					
						
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										 |  |  | 	char *isa_nm; | 
					
						
							|  |  |  | 	int i, be, atomic; | 
					
						
							|  |  |  | 	int n = 0; | 
					
						
							|  |  |  | 
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										 |  |  | 	FIX_PTR(cpu); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 	if (is_isa_arcompact()) { | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 		isa_nm = "ARCompact"; | 
					
						
							|  |  |  | 		be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 		atomic = cpu->isa.atomic1; | 
					
						
							|  |  |  | 		if (!cpu->isa.ver)	/* ISA BCR absent, use Kconfig info */ | 
					
						
							|  |  |  | 			atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC); | 
					
						
							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 	} else { | 
					
						
							|  |  |  | 		isa_nm = "ARCv2"; | 
					
						
							|  |  |  | 		be = cpu->isa.be; | 
					
						
							|  |  |  | 		atomic = cpu->isa.atomic; | 
					
						
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										 |  |  | 	} | 
					
						
							|  |  |  | 
 | 
					
						
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										 |  |  | 	n += scnprintf(buf + n, len - n, | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 		       "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n", | 
					
						
							|  |  |  | 		       core->family, core->cpu_id, core->chip_id); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) { | 
					
						
							|  |  |  | 		if ((core->family >= tbl->info.id) && | 
					
						
							|  |  |  | 		    (core->family <= tbl->up_range)) { | 
					
						
							|  |  |  | 			n += scnprintf(buf + n, len - n, | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 				       "processor [%d]\t: %s (%s ISA) %s\n", | 
					
						
							|  |  |  | 				       cpu_id, tbl->info.str, isa_nm, | 
					
						
							|  |  |  | 				       IS_AVAIL1(be, "[Big-Endian]")); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 			break; | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 	} | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	if (tbl->info.id == 0) | 
					
						
							|  |  |  | 		n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n"); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n", | 
					
						
							|  |  |  | 		       (unsigned int)(arc_get_core_freq() / 1000000), | 
					
						
							|  |  |  | 		       (unsigned int)(arc_get_core_freq() / 10000) % 100); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-11-07 14:57:16 +05:30
										 |  |  | 	n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ", | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 		       IS_AVAIL1(cpu->timers.t0, "Timer0 "), | 
					
						
							| 
									
										
										
										
											2013-11-07 14:57:16 +05:30
										 |  |  | 		       IS_AVAIL1(cpu->timers.t1, "Timer1 "), | 
					
						
							|  |  |  | 		       IS_AVAIL2(cpu->timers.rtc, "64-bit RTC ", | 
					
						
							|  |  |  | 				 CONFIG_ARC_HAS_RTC)); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 	n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s", | 
					
						
							|  |  |  | 			   IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC), | 
					
						
							|  |  |  | 			   IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64), | 
					
						
							|  |  |  | 			   IS_AVAIL1(cpu->isa.unalign, "unalign (not used)")); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	if (i) | 
					
						
							|  |  |  | 		n += scnprintf(buf + n, len - n, "\n\t\t: "); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 	if (cpu->extn_mpy.ver) { | 
					
						
							|  |  |  | 		if (cpu->extn_mpy.ver <= 0x2) {	/* ARCompact */ | 
					
						
							|  |  |  | 			n += scnprintf(buf + n, len - n, "mpy "); | 
					
						
							|  |  |  | 		} else { | 
					
						
							|  |  |  | 			int opt = 2;	/* stock MPY/MPYH */ | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 			if (cpu->extn_mpy.dsp)	/* OPT 7-9 */ | 
					
						
							|  |  |  | 				opt = cpu->extn_mpy.dsp + 6; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 			n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt); | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 		n += scnprintf(buf + n, len - n, "%s", | 
					
						
							| 
									
										
										
										
											2015-07-06 15:25:21 +05:30
										 |  |  | 			       IS_USED_CFG(CONFIG_ARC_HAS_HW_MPY)); | 
					
						
							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 	} | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n", | 
					
						
							| 
									
										
										
											
												ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are:
    - SMP configurations of upto 4 cores with coherency
    - Optional L2 Cache and IO-Coherency
    - Revised Interrupt Architecture (multiple priorites, reg banks,
        auto stack switch, auto regfile save/restore)
    - MMUv4 (PIPT dcache, Huge Pages)
    - Instructions for
	* 64bit load/store: LDD, STD
	* Hardware assisted divide/remainder: DIV, REM
	* Function prologue/epilogue: ENTER_S, LEAVE_S
	* IRQ enable/disable: CLRI, SETI
	* pop count: FFS, FLS
	* SETcc, BMSKN, XBFU...
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
											
										 
											2013-05-13 18:30:41 +05:30
										 |  |  | 		       IS_AVAIL1(cpu->isa.div_rem, "div_rem "), | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 		       IS_AVAIL1(cpu->extn.norm, "norm "), | 
					
						
							|  |  |  | 		       IS_AVAIL1(cpu->extn.barrel, "barrel-shift "), | 
					
						
							|  |  |  | 		       IS_AVAIL1(cpu->extn.swap, "swap "), | 
					
						
							|  |  |  | 		       IS_AVAIL1(cpu->extn.minmax, "minmax "), | 
					
						
							|  |  |  | 		       IS_AVAIL1(cpu->extn.crc, "crc "), | 
					
						
							|  |  |  | 		       IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE)); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	if (cpu->bpu.ver) | 
					
						
							|  |  |  | 		n += scnprintf(buf + n, len - n, | 
					
						
							|  |  |  | 			      "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n", | 
					
						
							|  |  |  | 			      IS_AVAIL1(cpu->bpu.full, "full"), | 
					
						
							|  |  |  | 			      IS_AVAIL1(!cpu->bpu.full, "partial"), | 
					
						
							|  |  |  | 			      cpu->bpu.num_cache, cpu->bpu.num_pred); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	return buf; | 
					
						
							|  |  |  | } | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-09-04 16:13:35 +05:30
										 |  |  | static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len) | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | { | 
					
						
							|  |  |  | 	int n = 0; | 
					
						
							|  |  |  | 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id]; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	FIX_PTR(cpu); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	n += scnprintf(buf + n, len - n, | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 		       "Vector Table\t: %#x\nUncached Base\t: %#x\n", | 
					
						
							| 
									
										
										
										
											2015-04-16 19:49:12 +05:30
										 |  |  | 		       cpu->vec_base, ARC_UNCACHED_ADDR_SPACE); | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	if (cpu->extn.fpu_sp || cpu->extn.fpu_dp) | 
					
						
							|  |  |  | 		n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n", | 
					
						
							|  |  |  | 			       IS_AVAIL1(cpu->extn.fpu_sp, "SP "), | 
					
						
							|  |  |  | 			       IS_AVAIL1(cpu->extn.fpu_dp, "DP ")); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	if (cpu->extn.debug) | 
					
						
							|  |  |  | 		n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n", | 
					
						
							|  |  |  | 			       IS_AVAIL1(cpu->extn.ap, "ActionPoint "), | 
					
						
							|  |  |  | 			       IS_AVAIL1(cpu->extn.smart, "smaRT "), | 
					
						
							|  |  |  | 			       IS_AVAIL1(cpu->extn.rtt, "RTT ")); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	if (cpu->dccm.sz || cpu->iccm.sz) | 
					
						
							|  |  |  | 		n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n", | 
					
						
							|  |  |  | 			       cpu->dccm.base_addr, TO_KB(cpu->dccm.sz), | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 			       cpu->iccm.base_addr, TO_KB(cpu->iccm.sz)); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	n += scnprintf(buf + n, len - n, | 
					
						
							| 
									
										
										
										
											2013-03-06 14:33:27 +05:30
										 |  |  | 		       "OS ABI [v3]\t: no-legacy-syscalls\n"); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	return buf; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:07:44 +05:30
										 |  |  | static void arc_chk_core_config(void) | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:25 +05:30
										 |  |  | { | 
					
						
							|  |  |  | 	struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()]; | 
					
						
							| 
									
										
										
										
											2014-09-25 16:07:44 +05:30
										 |  |  | 	int fpu_enabled; | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:25 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	if (!cpu->timers.t0) | 
					
						
							|  |  |  | 		panic("Timer0 is not present!\n"); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	if (!cpu->timers.t1) | 
					
						
							|  |  |  | 		panic("Timer1 is not present!\n"); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-11-07 14:57:16 +05:30
										 |  |  | 	if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->timers.rtc) | 
					
						
							|  |  |  | 		panic("RTC is not present\n"); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:25 +05:30
										 |  |  | #ifdef CONFIG_ARC_HAS_DCCM
 | 
					
						
							|  |  |  | 	/*
 | 
					
						
							|  |  |  | 	 * DCCM can be arbit placed in hardware. | 
					
						
							|  |  |  | 	 * Make sure it's placement/sz matches what Linux is built with | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr) | 
					
						
							|  |  |  | 		panic("Linux built with incorrect DCCM Base address\n"); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz) | 
					
						
							|  |  |  | 		panic("Linux built with incorrect DCCM Size\n"); | 
					
						
							|  |  |  | #endif
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #ifdef CONFIG_ARC_HAS_ICCM
 | 
					
						
							|  |  |  | 	if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz) | 
					
						
							|  |  |  | 		panic("Linux built with incorrect ICCM Size\n"); | 
					
						
							|  |  |  | #endif
 | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:07:44 +05:30
										 |  |  | 	/*
 | 
					
						
							|  |  |  | 	 * FP hardware/software config sanity | 
					
						
							|  |  |  | 	 * -If hardware contains DPFP, kernel needs to save/restore FPU state | 
					
						
							|  |  |  | 	 * -If not, it will crash trying to save/restore the non-existant regs | 
					
						
							|  |  |  | 	 * | 
					
						
							|  |  |  | 	 * (only DPDP checked since SP has no arch visible regs) | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	if (cpu->extn.fpu_dp && !fpu_enabled) | 
					
						
							| 
									
										
										
										
											2014-09-25 16:07:44 +05:30
										 |  |  | 		pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n"); | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	else if (!cpu->extn.fpu_dp && fpu_enabled) | 
					
						
							| 
									
										
										
										
											2014-09-25 16:07:44 +05:30
										 |  |  | 		panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n"); | 
					
						
							| 
									
										
										
										
											2015-07-14 19:50:18 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	if (is_isa_arcv2() && IS_ENABLED(CONFIG_SMP) && cpu->isa.atomic && | 
					
						
							|  |  |  | 	    !IS_ENABLED(CONFIG_ARC_STAR_9000923308)) | 
					
						
							|  |  |  | 		panic("llock/scond livelock workaround missing\n"); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Initialize and setup the processor core | 
					
						
							|  |  |  |  * This is called by all the CPUs thus should not do special case stuff | 
					
						
							|  |  |  |  *    such as only for boot CPU etc | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-06-24 15:30:15 -04:00
										 |  |  | void setup_processor(void) | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | { | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 	char str[512]; | 
					
						
							|  |  |  | 	int cpu_id = smp_processor_id(); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 	read_arc_build_cfg_regs(); | 
					
						
							|  |  |  | 	arc_init_IRQ(); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str))); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 	arc_mmu_init(); | 
					
						
							|  |  |  | 	arc_cache_init(); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str))); | 
					
						
							|  |  |  | 	printk(arc_platform_smp_cpuinfo()); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:07:44 +05:30
										 |  |  | 	arc_chk_core_config(); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-01-16 15:01:24 +05:30
										 |  |  | static inline int is_kernel(unsigned long addr) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end) | 
					
						
							|  |  |  | 		return 1; | 
					
						
							|  |  |  | 	return 0; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | void __init setup_arch(char **cmdline_p) | 
					
						
							|  |  |  | { | 
					
						
							| 
									
										
										
										
											2015-03-09 19:40:09 +05:30
										 |  |  | #ifdef CONFIG_ARC_UBOOT_SUPPORT
 | 
					
						
							| 
									
										
										
										
											2014-01-16 15:04:24 +05:30
										 |  |  | 	/* make sure that uboot passed pointer to cmdline/dtb is valid */ | 
					
						
							|  |  |  | 	if (uboot_tag && is_kernel((unsigned long)uboot_arg)) | 
					
						
							|  |  |  | 		panic("Invalid uboot arg\n"); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	/* See if u-boot passed an external Device Tree blob */ | 
					
						
							|  |  |  | 	machine_desc = setup_machine_fdt(uboot_arg);	/* uboot_tag == 2 */ | 
					
						
							| 
									
										
										
										
											2015-03-09 19:40:09 +05:30
										 |  |  | 	if (!machine_desc) | 
					
						
							|  |  |  | #endif
 | 
					
						
							|  |  |  | 	{ | 
					
						
							| 
									
										
										
										
											2014-01-16 15:04:24 +05:30
										 |  |  | 		/* No, so try the embedded one */ | 
					
						
							| 
									
										
										
										
											2014-01-16 15:01:24 +05:30
										 |  |  | 		machine_desc = setup_machine_fdt(__dtb_start); | 
					
						
							|  |  |  | 		if (!machine_desc) | 
					
						
							|  |  |  | 			panic("Embedded DT invalid\n"); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 		/*
 | 
					
						
							| 
									
										
										
										
											2014-01-16 15:04:24 +05:30
										 |  |  | 		 * If we are here, it is established that @uboot_arg didn't | 
					
						
							|  |  |  | 		 * point to DT blob. Instead if u-boot says it is cmdline, | 
					
						
							|  |  |  | 		 * Appent to embedded DT cmdline. | 
					
						
							| 
									
										
										
										
											2014-01-16 15:01:24 +05:30
										 |  |  | 		 * setup_machine_fdt() would have populated @boot_command_line | 
					
						
							|  |  |  | 		 */ | 
					
						
							|  |  |  | 		if (uboot_tag == 1) { | 
					
						
							|  |  |  | 			/* Ensure a whitespace between the 2 cmdlines */ | 
					
						
							|  |  |  | 			strlcat(boot_command_line, " ", COMMAND_LINE_SIZE); | 
					
						
							|  |  |  | 			strlcat(boot_command_line, uboot_arg, | 
					
						
							|  |  |  | 				COMMAND_LINE_SIZE); | 
					
						
							|  |  |  | 		} | 
					
						
							| 
									
										
										
										
											2014-01-16 15:04:24 +05:30
										 |  |  | 	} | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	/* Save unparsed command line copy for /proc/cmdline */ | 
					
						
							| 
									
										
										
										
											2013-04-09 16:18:04 +05:30
										 |  |  | 	*cmdline_p = boot_command_line; | 
					
						
							| 
									
										
										
										
											2013-01-22 17:00:52 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 	/* To force early parsing of things like mem=xxx */ | 
					
						
							|  |  |  | 	parse_early_param(); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	/* Platform/board specific: e.g. early console registration */ | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:26 +05:30
										 |  |  | 	if (machine_desc->init_early) | 
					
						
							|  |  |  | 		machine_desc->init_early(); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	setup_processor(); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:23 +05:30
										 |  |  | 	smp_init_cpus(); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 	setup_arch_memory(); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-02-21 17:37:06 +05:30
										 |  |  | 	/* copy flat DT out of .init and then unflatten it */ | 
					
						
							| 
									
										
										
										
											2013-08-26 11:23:27 -05:00
										 |  |  | 	unflatten_and_copy_device_tree(); | 
					
						
							| 
									
										
										
										
											2013-01-22 17:00:52 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 	/* Can be issue if someone passes cmd line arg "ro"
 | 
					
						
							|  |  |  | 	 * But that is unlikely so keeping it as it is | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	root_mountflags &= ~MS_RDONLY; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
 | 
					
						
							|  |  |  | 	conswitchp = &dummy_con; | 
					
						
							|  |  |  | #endif
 | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-22 17:03:19 +05:30
										 |  |  | 	arc_unwind_init(); | 
					
						
							|  |  |  | 	arc_unwind_setup(); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:26 +05:30
										 |  |  | static int __init customize_machine(void) | 
					
						
							|  |  |  | { | 
					
						
							| 
									
										
										
										
											2014-09-10 11:10:54 +05:30
										 |  |  | 	of_clk_init(NULL); | 
					
						
							|  |  |  | 	/*
 | 
					
						
							|  |  |  | 	 * Traverses flattened DeviceTree - registering platform devices | 
					
						
							|  |  |  | 	 * (if any) complete with their resources | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:26 +05:30
										 |  |  | 	if (machine_desc->init_machine) | 
					
						
							|  |  |  | 		machine_desc->init_machine(); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	return 0; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | arch_initcall(customize_machine); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | static int __init init_late_machine(void) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	if (machine_desc->init_late) | 
					
						
							|  |  |  | 		machine_desc->init_late(); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	return 0; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | late_initcall(init_late_machine); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | /*
 | 
					
						
							|  |  |  |  *  Get CPU information for use by the procfs. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #define cpu_to_ptr(c)	((void *)(0xFFFF0000 | (unsigned int)(c)))
 | 
					
						
							|  |  |  | #define ptr_to_cpu(p)	(~0xFFFF0000UL & (unsigned int)(p))
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | static int show_cpuinfo(struct seq_file *m, void *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	char *str; | 
					
						
							|  |  |  | 	int cpu_id = ptr_to_cpu(v); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-12-12 10:05:03 +05:30
										 |  |  | 	if (!cpu_online(cpu_id)) { | 
					
						
							|  |  |  | 		seq_printf(m, "processor [%d]\t: Offline\n", cpu_id); | 
					
						
							|  |  |  | 		goto done; | 
					
						
							|  |  |  | 	} | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 	str = (char *)__get_free_page(GFP_TEMPORARY); | 
					
						
							|  |  |  | 	if (!str) | 
					
						
							|  |  |  | 		goto done; | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 	seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE)); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2014-09-25 16:54:43 +05:30
										 |  |  | 	seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n", | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 		   loops_per_jiffy / (500000 / HZ), | 
					
						
							|  |  |  | 		   (loops_per_jiffy / (5000 / HZ)) % 100); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:24 +05:30
										 |  |  | 	seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE)); | 
					
						
							|  |  |  | 	seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE)); | 
					
						
							|  |  |  | 	seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE)); | 
					
						
							|  |  |  | 	seq_printf(m, arc_platform_smp_cpuinfo()); | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 	free_page((unsigned long)str); | 
					
						
							|  |  |  | done: | 
					
						
							| 
									
										
										
										
											2014-12-12 10:05:03 +05:30
										 |  |  | 	seq_printf(m, "\n"); | 
					
						
							| 
									
										
										
										
											2013-01-18 15:12:20 +05:30
										 |  |  | 
 | 
					
						
							|  |  |  | 	return 0; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | static void *c_start(struct seq_file *m, loff_t *pos) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	/*
 | 
					
						
							|  |  |  | 	 * Callback returns cpu-id to iterator for show routine, NULL to stop. | 
					
						
							|  |  |  | 	 * However since NULL is also a valid cpu-id (0), we use a round-about | 
					
						
							|  |  |  | 	 * way to pass it w/o having to kmalloc/free a 2 byte string. | 
					
						
							|  |  |  | 	 * Encode cpu-id as 0xFFcccc, which is decoded by show routine. | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | static void *c_next(struct seq_file *m, void *v, loff_t *pos) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	++*pos; | 
					
						
							|  |  |  | 	return c_start(m, pos); | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | static void c_stop(struct seq_file *m, void *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | const struct seq_operations cpuinfo_op = { | 
					
						
							|  |  |  | 	.start	= c_start, | 
					
						
							|  |  |  | 	.next	= c_next, | 
					
						
							|  |  |  | 	.stop	= c_stop, | 
					
						
							|  |  |  | 	.show	= show_cpuinfo | 
					
						
							|  |  |  | }; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | static DEFINE_PER_CPU(struct cpu, cpu_topology); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | static int __init topology_init(void) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	int cpu; | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	for_each_present_cpu(cpu) | 
					
						
							|  |  |  | 	    register_cpu(&per_cpu(cpu_topology, cpu), cpu); | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	return 0; | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | subsys_initcall(topology_init); |