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										 |  |  | /*
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							|  |  |  |  * This header provides macros for ams AS3722 device bindings. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Copyright (c) 2013, NVIDIA Corporation. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Author: Laxman Dewangan <ldewangan@nvidia.com> | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | #ifndef __DT_BINDINGS_AS3722_H__
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							|  |  |  | #define __DT_BINDINGS_AS3722_H__
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							|  |  |  | /* External control pins */ | 
					
						
							|  |  |  | #define AS3722_EXT_CONTROL_PIN_ENABLE1 1
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							|  |  |  | #define AS3722_EXT_CONTROL_PIN_ENABLE2 2
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										 |  |  | #define AS3722_EXT_CONTROL_PIN_ENABLE3 3
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							|  |  |  | /* Interrupt numbers for AS3722 */ | 
					
						
							|  |  |  | #define AS3722_IRQ_LID			0
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							|  |  |  | #define AS3722_IRQ_ACOK			1
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							|  |  |  | #define AS3722_IRQ_ENABLE1		2
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							|  |  |  | #define AS3722_IRQ_OCCUR_ALARM_SD0	3
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							|  |  |  | #define AS3722_IRQ_ONKEY_LONG_PRESS	4
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							|  |  |  | #define AS3722_IRQ_ONKEY		5
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							|  |  |  | #define AS3722_IRQ_OVTMP		6
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							|  |  |  | #define AS3722_IRQ_LOWBAT		7
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							|  |  |  | #define AS3722_IRQ_SD0_LV		8
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							|  |  |  | #define AS3722_IRQ_SD1_LV		9
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							|  |  |  | #define AS3722_IRQ_SD2_LV		10
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							|  |  |  | #define AS3722_IRQ_PWM1_OV_PROT		11
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							|  |  |  | #define AS3722_IRQ_PWM2_OV_PROT		12
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							|  |  |  | #define AS3722_IRQ_ENABLE2		13
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							|  |  |  | #define AS3722_IRQ_SD6_LV		14
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							|  |  |  | #define AS3722_IRQ_RTC_REP		15
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							|  |  |  | #define AS3722_IRQ_RTC_ALARM		16
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							|  |  |  | #define AS3722_IRQ_GPIO1		17
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							|  |  |  | #define AS3722_IRQ_GPIO2		18
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							|  |  |  | #define AS3722_IRQ_GPIO3		19
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							|  |  |  | #define AS3722_IRQ_GPIO4		20
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							|  |  |  | #define AS3722_IRQ_GPIO5		21
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							|  |  |  | #define AS3722_IRQ_WATCHDOG		22
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							|  |  |  | #define AS3722_IRQ_ENABLE3		23
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							|  |  |  | #define AS3722_IRQ_TEMP_SD0_SHUTDOWN	24
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							|  |  |  | #define AS3722_IRQ_TEMP_SD1_SHUTDOWN	25
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							|  |  |  | #define AS3722_IRQ_TEMP_SD2_SHUTDOWN	26
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							|  |  |  | #define AS3722_IRQ_TEMP_SD0_ALARM	27
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							|  |  |  | #define AS3722_IRQ_TEMP_SD1_ALARM	28
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							|  |  |  | #define AS3722_IRQ_TEMP_SD6_ALARM	29
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							|  |  |  | #define AS3722_IRQ_OCCUR_ALARM_SD6	30
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							|  |  |  | #define AS3722_IRQ_ADC			31
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							|  |  |  | #endif /* __DT_BINDINGS_AS3722_H__ */
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