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										 |  |  | /*
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							|  |  |  |  * Copyright 2013 Ideas On Board SPRL | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This program is free software; you can redistribute it and/or modify | 
					
						
							|  |  |  |  * it under the terms of the GNU General Public License as published by | 
					
						
							|  |  |  |  * the Free Software Foundation; either version 2 of the License, or | 
					
						
							|  |  |  |  * (at your option) any later version. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
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							|  |  |  | #ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
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							|  |  |  | #define __DT_BINDINGS_CLOCK_R8A7790_H__
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							|  |  |  | /* CPG */ | 
					
						
							|  |  |  | #define R8A7790_CLK_MAIN		0
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							|  |  |  | #define R8A7790_CLK_PLL0		1
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							|  |  |  | #define R8A7790_CLK_PLL1		2
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							|  |  |  | #define R8A7790_CLK_PLL3		3
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							|  |  |  | #define R8A7790_CLK_LB			4
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							|  |  |  | #define R8A7790_CLK_QSPI		5
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							|  |  |  | #define R8A7790_CLK_SDH			6
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							|  |  |  | #define R8A7790_CLK_SD0			7
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							|  |  |  | #define R8A7790_CLK_SD1			8
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							|  |  |  | #define R8A7790_CLK_Z			9
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										 |  |  | /* MSTP0 */ | 
					
						
							|  |  |  | #define R8A7790_CLK_MSIOF0		0
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										 |  |  | /* MSTP1 */ | 
					
						
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										 |  |  | #define R8A7790_CLK_VCP1		0
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							|  |  |  | #define R8A7790_CLK_VCP0		1
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							|  |  |  | #define R8A7790_CLK_VPC1		2
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							|  |  |  | #define R8A7790_CLK_VPC0		3
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							|  |  |  | #define R8A7790_CLK_JPU			6
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							|  |  |  | #define R8A7790_CLK_SSP1		9
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										 |  |  | #define R8A7790_CLK_TMU1		11
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										 |  |  | #define R8A7790_CLK_3DG			12
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										 |  |  | #define R8A7790_CLK_2DDMAC		15
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							|  |  |  | #define R8A7790_CLK_FDP1_2		17
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							|  |  |  | #define R8A7790_CLK_FDP1_1		18
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							|  |  |  | #define R8A7790_CLK_FDP1_0		19
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										 |  |  | #define R8A7790_CLK_TMU3		21
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							|  |  |  | #define R8A7790_CLK_TMU2		22
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							|  |  |  | #define R8A7790_CLK_CMT0		24
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							|  |  |  | #define R8A7790_CLK_TMU0		25
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							|  |  |  | #define R8A7790_CLK_VSP1_DU1		27
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							|  |  |  | #define R8A7790_CLK_VSP1_DU0		28
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										 |  |  | #define R8A7790_CLK_VSP1_R		30
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							|  |  |  | #define R8A7790_CLK_VSP1_S		31
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							|  |  |  | /* MSTP2 */ | 
					
						
							|  |  |  | #define R8A7790_CLK_SCIFA2		2
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							|  |  |  | #define R8A7790_CLK_SCIFA1		3
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							|  |  |  | #define R8A7790_CLK_SCIFA0		4
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										 |  |  | #define R8A7790_CLK_MSIOF2		5
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										 |  |  | #define R8A7790_CLK_SCIFB0		6
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							|  |  |  | #define R8A7790_CLK_SCIFB1		7
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										 |  |  | #define R8A7790_CLK_MSIOF1		8
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							|  |  |  | #define R8A7790_CLK_MSIOF3		15
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										 |  |  | #define R8A7790_CLK_SCIFB2		16
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										 |  |  | #define R8A7790_CLK_SYS_DMAC1		18
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							|  |  |  | #define R8A7790_CLK_SYS_DMAC0		19
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							|  |  |  | /* MSTP3 */ | 
					
						
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										 |  |  | #define R8A7790_CLK_IIC2		0
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										 |  |  | #define R8A7790_CLK_TPU0		4
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							|  |  |  | #define R8A7790_CLK_MMCIF1		5
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							|  |  |  | #define R8A7790_CLK_SDHI3		11
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							|  |  |  | #define R8A7790_CLK_SDHI2		12
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							|  |  |  | #define R8A7790_CLK_SDHI1		13
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							|  |  |  | #define R8A7790_CLK_SDHI0		14
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							|  |  |  | #define R8A7790_CLK_MMCIF0		15
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										 |  |  | #define R8A7790_CLK_IIC0		18
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										 |  |  | #define R8A7790_CLK_PCIEC		19
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										 |  |  | #define R8A7790_CLK_IIC1		23
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										 |  |  | #define R8A7790_CLK_SSUSB		28
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							|  |  |  | #define R8A7790_CLK_CMT1		29
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							|  |  |  | #define R8A7790_CLK_USBDMAC0		30
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							|  |  |  | #define R8A7790_CLK_USBDMAC1		31
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							|  |  |  | /* MSTP5 */ | 
					
						
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										 |  |  | #define R8A7790_CLK_AUDIO_DMAC1		1
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							|  |  |  | #define R8A7790_CLK_AUDIO_DMAC0		2
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										 |  |  | #define R8A7790_CLK_THERMAL		22
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							|  |  |  | #define R8A7790_CLK_PWM			23
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							|  |  |  | /* MSTP7 */ | 
					
						
							|  |  |  | #define R8A7790_CLK_EHCI		3
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							|  |  |  | #define R8A7790_CLK_HSUSB		4
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							|  |  |  | #define R8A7790_CLK_HSCIF1		16
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							|  |  |  | #define R8A7790_CLK_HSCIF0		17
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							|  |  |  | #define R8A7790_CLK_SCIF1		20
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							|  |  |  | #define R8A7790_CLK_SCIF0		21
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							|  |  |  | #define R8A7790_CLK_DU2			22
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							|  |  |  | #define R8A7790_CLK_DU1			23
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							|  |  |  | #define R8A7790_CLK_DU0			24
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							|  |  |  | #define R8A7790_CLK_LVDS1		25
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							|  |  |  | #define R8A7790_CLK_LVDS0		26
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							|  |  |  | /* MSTP8 */ | 
					
						
							|  |  |  | #define R8A7790_CLK_VIN3		8
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							|  |  |  | #define R8A7790_CLK_VIN2		9
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							|  |  |  | #define R8A7790_CLK_VIN1		10
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							|  |  |  | #define R8A7790_CLK_VIN0		11
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							|  |  |  | #define R8A7790_CLK_ETHER		13
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							|  |  |  | #define R8A7790_CLK_SATA1		14
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							|  |  |  | #define R8A7790_CLK_SATA0		15
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							|  |  |  | /* MSTP9 */ | 
					
						
							|  |  |  | #define R8A7790_CLK_GPIO5		7
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							|  |  |  | #define R8A7790_CLK_GPIO4		8
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							|  |  |  | #define R8A7790_CLK_GPIO3		9
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							|  |  |  | #define R8A7790_CLK_GPIO2		10
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							|  |  |  | #define R8A7790_CLK_GPIO1		11
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							|  |  |  | #define R8A7790_CLK_GPIO0		12
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							|  |  |  | #define R8A7790_CLK_RCAN1		15
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							|  |  |  | #define R8A7790_CLK_RCAN0		16
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										 |  |  | #define R8A7790_CLK_QSPI_MOD		17
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										 |  |  | #define R8A7790_CLK_IICDVFS		26
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							|  |  |  | #define R8A7790_CLK_I2C3		28
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							|  |  |  | #define R8A7790_CLK_I2C2		29
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							|  |  |  | #define R8A7790_CLK_I2C1		30
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							|  |  |  | #define R8A7790_CLK_I2C0		31
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										 |  |  | /* MSTP10 */ | 
					
						
							|  |  |  | #define R8A7790_CLK_SSI_ALL		5
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							|  |  |  | #define R8A7790_CLK_SSI9		6
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							|  |  |  | #define R8A7790_CLK_SSI8		7
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							|  |  |  | #define R8A7790_CLK_SSI7		8
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							|  |  |  | #define R8A7790_CLK_SSI6		9
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							|  |  |  | #define R8A7790_CLK_SSI5		10
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							|  |  |  | #define R8A7790_CLK_SSI4		11
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							|  |  |  | #define R8A7790_CLK_SSI3		12
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							|  |  |  | #define R8A7790_CLK_SSI2		13
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							|  |  |  | #define R8A7790_CLK_SSI1		14
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							|  |  |  | #define R8A7790_CLK_SSI0		15
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							|  |  |  | #define R8A7790_CLK_SCU_ALL		17
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							|  |  |  | #define R8A7790_CLK_SCU_DVC1		18
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							|  |  |  | #define R8A7790_CLK_SCU_DVC0		19
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							|  |  |  | #define R8A7790_CLK_SCU_SRC9		22
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							|  |  |  | #define R8A7790_CLK_SCU_SRC8		23
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							|  |  |  | #define R8A7790_CLK_SCU_SRC7		24
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							|  |  |  | #define R8A7790_CLK_SCU_SRC6		25
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							|  |  |  | #define R8A7790_CLK_SCU_SRC5		26
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							|  |  |  | #define R8A7790_CLK_SCU_SRC4		27
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							|  |  |  | #define R8A7790_CLK_SCU_SRC3		28
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							|  |  |  | #define R8A7790_CLK_SCU_SRC2		29
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							|  |  |  | #define R8A7790_CLK_SCU_SRC1		30
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							|  |  |  | #define R8A7790_CLK_SCU_SRC0		31
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										 |  |  | #endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
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