2007-01-21 15:56:10 -03:00
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/*
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* Driver for Quantek QT1010 silicon tuner
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*
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* Copyright (C) 2006 Antti Palosaari <crope@iki.fi>
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* Aapo Tahkola <aet@rasterburn.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include "qt1010.h"
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#include "qt1010_priv.h"
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/* read single register */
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static int qt1010_readreg(struct qt1010_priv *priv, u8 reg, u8 *val)
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{
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struct i2c_msg msg[2] = {
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2007-02-13 18:26:26 -03:00
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{ .addr = priv->cfg->i2c_address,
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.flags = 0, .buf = ®, .len = 1 },
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{ .addr = priv->cfg->i2c_address,
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.flags = I2C_M_RD, .buf = val, .len = 1 },
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2007-01-21 15:56:10 -03:00
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};
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if (i2c_transfer(priv->i2c, msg, 2) != 2) {
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2012-08-21 10:18:58 -03:00
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dev_warn(&priv->i2c->dev, "%s: i2c rd failed reg=%02x\n",
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KBUILD_MODNAME, reg);
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2007-01-21 15:56:10 -03:00
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return -EREMOTEIO;
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}
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return 0;
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}
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/* write single register */
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static int qt1010_writereg(struct qt1010_priv *priv, u8 reg, u8 val)
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{
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u8 buf[2] = { reg, val };
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2007-02-13 18:26:26 -03:00
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struct i2c_msg msg = { .addr = priv->cfg->i2c_address,
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.flags = 0, .buf = buf, .len = 2 };
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2007-01-21 15:56:10 -03:00
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if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
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2012-08-21 10:18:58 -03:00
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dev_warn(&priv->i2c->dev, "%s: i2c wr failed reg=%02x\n",
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KBUILD_MODNAME, reg);
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2007-01-21 15:56:10 -03:00
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return -EREMOTEIO;
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}
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return 0;
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}
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2011-12-24 12:24:33 -03:00
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static int qt1010_set_params(struct dvb_frontend *fe)
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2007-01-21 15:56:10 -03:00
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{
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2011-12-21 07:39:33 -03:00
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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2007-01-21 15:56:10 -03:00
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struct qt1010_priv *priv;
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int err;
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u32 freq, div, mod1, mod2;
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u8 i, tmpval, reg05;
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qt1010_i2c_oper_t rd[48] = {
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{ QT1010_WR, 0x01, 0x80 },
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{ QT1010_WR, 0x02, 0x3f },
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{ QT1010_WR, 0x05, 0xff }, /* 02 c write */
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{ QT1010_WR, 0x06, 0x44 },
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{ QT1010_WR, 0x07, 0xff }, /* 04 c write */
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{ QT1010_WR, 0x08, 0x08 },
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{ QT1010_WR, 0x09, 0xff }, /* 06 c write */
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{ QT1010_WR, 0x0a, 0xff }, /* 07 c write */
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{ QT1010_WR, 0x0b, 0xff }, /* 08 c write */
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{ QT1010_WR, 0x0c, 0xe1 },
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{ QT1010_WR, 0x1a, 0xff }, /* 10 c write */
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{ QT1010_WR, 0x1b, 0x00 },
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{ QT1010_WR, 0x1c, 0x89 },
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{ QT1010_WR, 0x11, 0xff }, /* 13 c write */
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{ QT1010_WR, 0x12, 0xff }, /* 14 c write */
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{ QT1010_WR, 0x22, 0xff }, /* 15 c write */
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{ QT1010_WR, 0x1e, 0x00 },
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{ QT1010_WR, 0x1e, 0xd0 },
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{ QT1010_RD, 0x22, 0xff }, /* 16 c read */
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{ QT1010_WR, 0x1e, 0x00 },
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{ QT1010_RD, 0x05, 0xff }, /* 20 c read */
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{ QT1010_RD, 0x22, 0xff }, /* 21 c read */
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{ QT1010_WR, 0x23, 0xd0 },
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{ QT1010_WR, 0x1e, 0x00 },
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{ QT1010_WR, 0x1e, 0xe0 },
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{ QT1010_RD, 0x23, 0xff }, /* 25 c read */
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{ QT1010_RD, 0x23, 0xff }, /* 26 c read */
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{ QT1010_WR, 0x1e, 0x00 },
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{ QT1010_WR, 0x24, 0xd0 },
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{ QT1010_WR, 0x1e, 0x00 },
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{ QT1010_WR, 0x1e, 0xf0 },
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{ QT1010_RD, 0x24, 0xff }, /* 31 c read */
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{ QT1010_WR, 0x1e, 0x00 },
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{ QT1010_WR, 0x14, 0x7f },
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{ QT1010_WR, 0x15, 0x7f },
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{ QT1010_WR, 0x05, 0xff }, /* 35 c write */
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{ QT1010_WR, 0x06, 0x00 },
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{ QT1010_WR, 0x15, 0x1f },
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{ QT1010_WR, 0x16, 0xff },
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{ QT1010_WR, 0x18, 0xff },
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{ QT1010_WR, 0x1f, 0xff }, /* 40 c write */
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{ QT1010_WR, 0x20, 0xff }, /* 41 c write */
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{ QT1010_WR, 0x21, 0x53 },
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{ QT1010_WR, 0x25, 0xff }, /* 43 c write */
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{ QT1010_WR, 0x26, 0x15 },
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{ QT1010_WR, 0x00, 0xff }, /* 45 c write */
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{ QT1010_WR, 0x02, 0x00 },
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{ QT1010_WR, 0x01, 0x00 }
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};
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#define FREQ1 32000000 /* 32 MHz */
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#define FREQ2 4000000 /* 4 MHz Quartz oscillator in the stick? */
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priv = fe->tuner_priv;
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2011-12-21 07:39:33 -03:00
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freq = c->frequency;
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2007-01-21 15:56:10 -03:00
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div = (freq + QT1010_OFFSET) / QT1010_STEP;
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freq = (div * QT1010_STEP) - QT1010_OFFSET;
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mod1 = (freq + QT1010_OFFSET) % FREQ1;
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mod2 = (freq + QT1010_OFFSET) % FREQ2;
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priv->frequency = freq;
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2007-01-27 16:41:35 -03:00
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
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2007-01-21 15:56:10 -03:00
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/* reg 05 base value */
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if (freq < 290000000) reg05 = 0x14; /* 290 MHz */
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else if (freq < 610000000) reg05 = 0x34; /* 610 MHz */
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else if (freq < 802000000) reg05 = 0x54; /* 802 MHz */
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else reg05 = 0x74;
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/* 0x5 */
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rd[2].val = reg05;
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/* 07 - set frequency: 32 MHz scale */
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rd[4].val = (freq + QT1010_OFFSET) / FREQ1;
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/* 09 - changes every 8/24 MHz */
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if (mod1 < 8000000) rd[6].val = 0x1d;
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else rd[6].val = 0x1c;
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/* 0a - set frequency: 4 MHz scale (max 28 MHz) */
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if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */
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else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */
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else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */
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else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */
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else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */
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else if (mod1 < 6*FREQ2) rd[7].val = 0x0c; /* +20 MHz */
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else if (mod1 < 7*FREQ2) rd[7].val = 0x0b; /* +24 MHz */
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else rd[7].val = 0x0a; /* +28 MHz */
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/* 0b - changes every 2/2 MHz */
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if (mod2 < 2000000) rd[8].val = 0x45;
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else rd[8].val = 0x44;
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/* 1a - set frequency: 125 kHz scale (max 3875 kHz)*/
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tmpval = 0x78; /* byte, overflows intentionally */
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rd[10].val = tmpval-((mod2/QT1010_STEP)*0x08);
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/* 11 */
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rd[13].val = 0xfd; /* TODO: correct value calculation */
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/* 12 */
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rd[14].val = 0x91; /* TODO: correct value calculation */
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/* 22 */
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if (freq < 450000000) rd[15].val = 0xd0; /* 450 MHz */
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else if (freq < 482000000) rd[15].val = 0xd1; /* 482 MHz */
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else if (freq < 514000000) rd[15].val = 0xd4; /* 514 MHz */
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else if (freq < 546000000) rd[15].val = 0xd7; /* 546 MHz */
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else if (freq < 610000000) rd[15].val = 0xda; /* 610 MHz */
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else rd[15].val = 0xd0;
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/* 05 */
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rd[35].val = (reg05 & 0xf0);
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/* 1f */
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if (mod1 < 8000000) tmpval = 0x00;
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else if (mod1 < 12000000) tmpval = 0x01;
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else if (mod1 < 16000000) tmpval = 0x02;
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else if (mod1 < 24000000) tmpval = 0x03;
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else if (mod1 < 28000000) tmpval = 0x04;
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else tmpval = 0x05;
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rd[40].val = (priv->reg1f_init_val + 0x0e + tmpval);
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/* 20 */
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if (mod1 < 8000000) tmpval = 0x00;
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else if (mod1 < 12000000) tmpval = 0x01;
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else if (mod1 < 20000000) tmpval = 0x02;
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else if (mod1 < 24000000) tmpval = 0x03;
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else if (mod1 < 28000000) tmpval = 0x04;
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else tmpval = 0x05;
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rd[41].val = (priv->reg20_init_val + 0x0d + tmpval);
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/* 25 */
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rd[43].val = priv->reg25_init_val;
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/* 00 */
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rd[45].val = 0x92; /* TODO: correct value calculation */
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2012-08-21 10:18:58 -03:00
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dev_dbg(&priv->i2c->dev,
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"%s: freq:%u 05:%02x 07:%02x 09:%02x 0a:%02x 0b:%02x " \
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"1a:%02x 11:%02x 12:%02x 22:%02x 05:%02x 1f:%02x " \
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"20:%02x 25:%02x 00:%02x\n", __func__, \
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freq, rd[2].val, rd[4].val, rd[6].val, rd[7].val, \
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rd[8].val, rd[10].val, rd[13].val, rd[14].val, \
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rd[15].val, rd[35].val, rd[40].val, rd[41].val, \
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rd[43].val, rd[45].val);
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2007-01-21 15:56:10 -03:00
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2007-02-13 17:53:46 -03:00
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for (i = 0; i < ARRAY_SIZE(rd); i++) {
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2007-01-21 15:56:10 -03:00
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if (rd[i].oper == QT1010_WR) {
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err = qt1010_writereg(priv, rd[i].reg, rd[i].val);
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} else { /* read is required to proper locking */
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err = qt1010_readreg(priv, rd[i].reg, &tmpval);
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}
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if (err) return err;
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}
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2007-01-27 16:41:35 -03:00
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
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2007-01-21 15:56:10 -03:00
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return 0;
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}
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2007-02-13 18:26:26 -03:00
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static int qt1010_init_meas1(struct qt1010_priv *priv,
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u8 oper, u8 reg, u8 reg_init_val, u8 *retval)
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2007-01-21 15:56:10 -03:00
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{
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u8 i, val1, val2;
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int err;
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qt1010_i2c_oper_t i2c_data[] = {
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{ QT1010_WR, reg, reg_init_val },
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{ QT1010_WR, 0x1e, 0x00 },
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{ QT1010_WR, 0x1e, oper },
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{ QT1010_RD, reg, 0xff }
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};
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2007-02-13 17:53:46 -03:00
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for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
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2007-01-21 15:56:10 -03:00
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if (i2c_data[i].oper == QT1010_WR) {
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2007-02-13 18:26:26 -03:00
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err = qt1010_writereg(priv, i2c_data[i].reg,
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i2c_data[i].val);
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2007-01-21 15:56:10 -03:00
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} else {
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err = qt1010_readreg(priv, i2c_data[i].reg, &val2);
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}
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if (err) return err;
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}
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do {
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val1 = val2;
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err = qt1010_readreg(priv, reg, &val2);
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if (err) return err;
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2012-08-21 10:18:58 -03:00
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dev_dbg(&priv->i2c->dev, "%s: compare reg:%02x %02x %02x\n",
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__func__, reg, val1, val2);
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2007-01-21 15:56:10 -03:00
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} while (val1 != val2);
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*retval = val1;
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return qt1010_writereg(priv, 0x1e, 0x00);
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}
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2012-08-10 05:25:03 -03:00
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static int qt1010_init_meas2(struct qt1010_priv *priv,
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2007-02-13 18:26:26 -03:00
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u8 reg_init_val, u8 *retval)
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2007-01-21 15:56:10 -03:00
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{
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u8 i, val;
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int err;
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|
|
|
qt1010_i2c_oper_t i2c_data[] = {
|
|
|
|
|
{ QT1010_WR, 0x07, reg_init_val },
|
|
|
|
|
{ QT1010_WR, 0x22, 0xd0 },
|
|
|
|
|
{ QT1010_WR, 0x1e, 0x00 },
|
|
|
|
|
{ QT1010_WR, 0x1e, 0xd0 },
|
|
|
|
|
{ QT1010_RD, 0x22, 0xff },
|
|
|
|
|
{ QT1010_WR, 0x1e, 0x00 },
|
|
|
|
|
{ QT1010_WR, 0x22, 0xff }
|
|
|
|
|
};
|
2007-02-13 17:53:46 -03:00
|
|
|
for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
|
2007-01-21 15:56:10 -03:00
|
|
|
if (i2c_data[i].oper == QT1010_WR) {
|
2007-02-13 18:26:26 -03:00
|
|
|
err = qt1010_writereg(priv, i2c_data[i].reg,
|
|
|
|
|
i2c_data[i].val);
|
2007-01-21 15:56:10 -03:00
|
|
|
} else {
|
|
|
|
|
err = qt1010_readreg(priv, i2c_data[i].reg, &val);
|
|
|
|
|
}
|
|
|
|
|
if (err) return err;
|
|
|
|
|
}
|
|
|
|
|
*retval = val;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int qt1010_init(struct dvb_frontend *fe)
|
|
|
|
|
{
|
|
|
|
|
struct qt1010_priv *priv = fe->tuner_priv;
|
2011-12-21 07:39:33 -03:00
|
|
|
struct dtv_frontend_properties *c = &fe->dtv_property_cache;
|
2007-02-13 16:46:13 -03:00
|
|
|
int err = 0;
|
2007-01-21 15:56:10 -03:00
|
|
|
u8 i, tmpval, *valptr = NULL;
|
|
|
|
|
|
|
|
|
|
qt1010_i2c_oper_t i2c_data[] = {
|
|
|
|
|
{ QT1010_WR, 0x01, 0x80 },
|
|
|
|
|
{ QT1010_WR, 0x0d, 0x84 },
|
|
|
|
|
{ QT1010_WR, 0x0e, 0xb7 },
|
|
|
|
|
{ QT1010_WR, 0x2a, 0x23 },
|
|
|
|
|
{ QT1010_WR, 0x2c, 0xdc },
|
|
|
|
|
{ QT1010_M1, 0x25, 0x40 }, /* get reg 25 init value */
|
|
|
|
|
{ QT1010_M1, 0x81, 0xff }, /* get reg 25 init value */
|
|
|
|
|
{ QT1010_WR, 0x2b, 0x70 },
|
|
|
|
|
{ QT1010_WR, 0x2a, 0x23 },
|
|
|
|
|
{ QT1010_M1, 0x26, 0x08 },
|
|
|
|
|
{ QT1010_M1, 0x82, 0xff },
|
|
|
|
|
{ QT1010_WR, 0x05, 0x14 },
|
|
|
|
|
{ QT1010_WR, 0x06, 0x44 },
|
|
|
|
|
{ QT1010_WR, 0x07, 0x28 },
|
|
|
|
|
{ QT1010_WR, 0x08, 0x0b },
|
|
|
|
|
{ QT1010_WR, 0x11, 0xfd },
|
|
|
|
|
{ QT1010_M1, 0x22, 0x0d },
|
|
|
|
|
{ QT1010_M1, 0xd0, 0xff },
|
|
|
|
|
{ QT1010_WR, 0x06, 0x40 },
|
|
|
|
|
{ QT1010_WR, 0x16, 0xf0 },
|
|
|
|
|
{ QT1010_WR, 0x02, 0x38 },
|
|
|
|
|
{ QT1010_WR, 0x03, 0x18 },
|
|
|
|
|
{ QT1010_WR, 0x20, 0xe0 },
|
|
|
|
|
{ QT1010_M1, 0x1f, 0x20 }, /* get reg 1f init value */
|
|
|
|
|
{ QT1010_M1, 0x84, 0xff }, /* get reg 1f init value */
|
|
|
|
|
{ QT1010_RD, 0x20, 0x20 }, /* get reg 20 init value */
|
|
|
|
|
{ QT1010_WR, 0x03, 0x19 },
|
|
|
|
|
{ QT1010_WR, 0x02, 0x3f },
|
|
|
|
|
{ QT1010_WR, 0x21, 0x53 },
|
|
|
|
|
{ QT1010_RD, 0x21, 0xff },
|
|
|
|
|
{ QT1010_WR, 0x11, 0xfd },
|
|
|
|
|
{ QT1010_WR, 0x05, 0x34 },
|
|
|
|
|
{ QT1010_WR, 0x06, 0x44 },
|
|
|
|
|
{ QT1010_WR, 0x08, 0x08 }
|
|
|
|
|
};
|
|
|
|
|
|
2007-01-27 16:41:35 -03:00
|
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
|
|
|
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
|
|
|
|
|
|
2007-02-13 17:53:46 -03:00
|
|
|
for (i = 0; i < ARRAY_SIZE(i2c_data); i++) {
|
2007-01-21 15:56:10 -03:00
|
|
|
switch (i2c_data[i].oper) {
|
|
|
|
|
case QT1010_WR:
|
2007-02-13 18:26:26 -03:00
|
|
|
err = qt1010_writereg(priv, i2c_data[i].reg,
|
|
|
|
|
i2c_data[i].val);
|
2007-01-21 15:56:10 -03:00
|
|
|
break;
|
|
|
|
|
case QT1010_RD:
|
2007-02-13 18:26:26 -03:00
|
|
|
if (i2c_data[i].val == 0x20)
|
|
|
|
|
valptr = &priv->reg20_init_val;
|
|
|
|
|
else
|
|
|
|
|
valptr = &tmpval;
|
2007-01-21 15:56:10 -03:00
|
|
|
err = qt1010_readreg(priv, i2c_data[i].reg, valptr);
|
|
|
|
|
break;
|
|
|
|
|
case QT1010_M1:
|
2007-02-13 18:26:26 -03:00
|
|
|
if (i2c_data[i].val == 0x25)
|
|
|
|
|
valptr = &priv->reg25_init_val;
|
|
|
|
|
else if (i2c_data[i].val == 0x1f)
|
|
|
|
|
valptr = &priv->reg1f_init_val;
|
|
|
|
|
else
|
|
|
|
|
valptr = &tmpval;
|
|
|
|
|
err = qt1010_init_meas1(priv, i2c_data[i+1].reg,
|
|
|
|
|
i2c_data[i].reg,
|
|
|
|
|
i2c_data[i].val, valptr);
|
2007-01-21 15:56:10 -03:00
|
|
|
i++;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if (err) return err;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (i = 0x31; i < 0x3a; i++) /* 0x31 - 0x39 */
|
|
|
|
|
if ((err = qt1010_init_meas2(priv, i, &tmpval)))
|
|
|
|
|
return err;
|
|
|
|
|
|
2012-08-21 09:08:20 -03:00
|
|
|
if (!c->frequency)
|
|
|
|
|
c->frequency = 545000000; /* Sigmatek DVB-110 545000000 */
|
2007-01-21 15:56:10 -03:00
|
|
|
/* MSI Megasky 580 GL861 533000000 */
|
2011-12-24 12:24:33 -03:00
|
|
|
return qt1010_set_params(fe);
|
2007-01-21 15:56:10 -03:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int qt1010_release(struct dvb_frontend *fe)
|
|
|
|
|
{
|
|
|
|
|
kfree(fe->tuner_priv);
|
|
|
|
|
fe->tuner_priv = NULL;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int qt1010_get_frequency(struct dvb_frontend *fe, u32 *frequency)
|
|
|
|
|
{
|
|
|
|
|
struct qt1010_priv *priv = fe->tuner_priv;
|
|
|
|
|
*frequency = priv->frequency;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-11-13 01:07:42 -03:00
|
|
|
static int qt1010_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
|
|
|
|
|
{
|
|
|
|
|
*frequency = 36125000;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2007-01-21 15:56:10 -03:00
|
|
|
static const struct dvb_tuner_ops qt1010_tuner_ops = {
|
|
|
|
|
.info = {
|
|
|
|
|
.name = "Quantek QT1010",
|
|
|
|
|
.frequency_min = QT1010_MIN_FREQ,
|
|
|
|
|
.frequency_max = QT1010_MAX_FREQ,
|
|
|
|
|
.frequency_step = QT1010_STEP,
|
|
|
|
|
},
|
|
|
|
|
|
|
|
|
|
.release = qt1010_release,
|
|
|
|
|
.init = qt1010_init,
|
|
|
|
|
/* TODO: implement sleep */
|
|
|
|
|
|
|
|
|
|
.set_params = qt1010_set_params,
|
|
|
|
|
.get_frequency = qt1010_get_frequency,
|
2011-11-13 01:07:42 -03:00
|
|
|
.get_if_frequency = qt1010_get_if_frequency,
|
2007-01-21 15:56:10 -03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct dvb_frontend * qt1010_attach(struct dvb_frontend *fe,
|
|
|
|
|
struct i2c_adapter *i2c,
|
|
|
|
|
struct qt1010_config *cfg)
|
|
|
|
|
{
|
|
|
|
|
struct qt1010_priv *priv = NULL;
|
|
|
|
|
u8 id;
|
|
|
|
|
|
|
|
|
|
priv = kzalloc(sizeof(struct qt1010_priv), GFP_KERNEL);
|
|
|
|
|
if (priv == NULL)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
2007-02-13 18:26:26 -03:00
|
|
|
priv->cfg = cfg;
|
|
|
|
|
priv->i2c = i2c;
|
2007-01-21 15:56:10 -03:00
|
|
|
|
2007-01-27 16:41:35 -03:00
|
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
|
|
|
fe->ops.i2c_gate_ctrl(fe, 1); /* open i2c_gate */
|
|
|
|
|
|
2007-01-21 15:56:10 -03:00
|
|
|
|
|
|
|
|
/* Try to detect tuner chip. Probably this is not correct register. */
|
|
|
|
|
if (qt1010_readreg(priv, 0x29, &id) != 0 || (id != 0x39)) {
|
|
|
|
|
kfree(priv);
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2007-01-27 16:41:35 -03:00
|
|
|
if (fe->ops.i2c_gate_ctrl)
|
|
|
|
|
fe->ops.i2c_gate_ctrl(fe, 0); /* close i2c_gate */
|
|
|
|
|
|
2012-08-21 10:18:58 -03:00
|
|
|
dev_info(&priv->i2c->dev,
|
|
|
|
|
"%s: Quantek QT1010 successfully identified\n",
|
|
|
|
|
KBUILD_MODNAME);
|
|
|
|
|
|
2007-02-13 18:26:26 -03:00
|
|
|
memcpy(&fe->ops.tuner_ops, &qt1010_tuner_ops,
|
|
|
|
|
sizeof(struct dvb_tuner_ops));
|
2007-01-21 15:56:10 -03:00
|
|
|
|
|
|
|
|
fe->tuner_priv = priv;
|
|
|
|
|
return fe;
|
|
|
|
|
}
|
|
|
|
|
EXPORT_SYMBOL(qt1010_attach);
|
|
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Quantek QT1010 silicon tuner driver");
|
|
|
|
|
MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
|
|
|
|
|
MODULE_AUTHOR("Aapo Tahkola <aet@rasterburn.org>");
|
|
|
|
|
MODULE_VERSION("0.1");
|
|
|
|
|
MODULE_LICENSE("GPL");
|
