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										 |  |  | /* $Id: jade.h,v 1.5.2.3 2004/01/14 16:04:48 keil Exp $
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							|  |  |  |  * | 
					
						
							|  |  |  |  * JADE specific defines | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Author       Roland Klabunde | 
					
						
							|  |  |  |  * Copyright    by Roland Klabunde   <R.Klabunde@Berkom.de> | 
					
						
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										 |  |  |  * | 
					
						
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										 |  |  |  * This software may be used and distributed according to the terms | 
					
						
							|  |  |  |  * of the GNU General Public License, incorporated herein by reference. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
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							|  |  |  | /* All Registers original Siemens Spec  */ | 
					
						
							|  |  |  | #ifndef	__JADE_H__
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							|  |  |  | #define	__JADE_H__
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							|  |  |  | /* Special registers for access to indirect accessible JADE regs */ | 
					
						
							|  |  |  | #define	DIRECT_IO_JADE	0x0000	/* Jade direct io access area */
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										 |  |  | #define	COMM_JADE	0x0040	/* Jade communication area */
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							|  |  |  | /********************************************************************/ | 
					
						
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										 |  |  | /* JADE-HDLC registers										    */ | 
					
						
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										 |  |  | /********************************************************************/ | 
					
						
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										 |  |  | #define jade_HDLC_RFIFO					0x00				   /* R */
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							|  |  |  | #define jade_HDLC_XFIFO					0x00				   /* W */
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							|  |  |  | #define	jade_HDLC_STAR					0x20				   /* R */
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							|  |  |  | #define	jadeSTAR_XDOV				0x80
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							|  |  |  | #define	jadeSTAR_XFW				0x40 /* Does not work*/
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							|  |  |  | #define	jadeSTAR_XCEC				0x20
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							|  |  |  | #define	jadeSTAR_RCEC				0x10
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							|  |  |  | #define	jadeSTAR_BSY				0x08
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							|  |  |  | #define	jadeSTAR_RNA				0x04
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							|  |  |  | #define	jadeSTAR_STR				0x02
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							|  |  |  | #define	jadeSTAR_STX				0x01
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							|  |  |  | #define	jade_HDLC_XCMD					0x20				   /* W */
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							|  |  |  | #define	jadeXCMD_XF				0x80
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							|  |  |  | #define	jadeXCMD_XME				0x40
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							|  |  |  | #define	jadeXCMD_XRES				0x20
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							|  |  |  | #define	jadeXCMD_STX				0x01
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							|  |  |  | #define	jade_HDLC_RSTA					0x21				   /* R */
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							|  |  |  | #define	jadeRSTA_VFR				0x80
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							|  |  |  | #define	jadeRSTA_RDO				0x40
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							|  |  |  | #define	jadeRSTA_CRC				0x20
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							|  |  |  | #define	jadeRSTA_RAB				0x10
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							|  |  |  | #define	jadeRSTA_MASK				0xF0
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							|  |  |  | #define	jade_HDLC_MODE					0x22				   /* RW*/
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										 |  |  | #define	jadeMODE_TMO				0x80
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							|  |  |  | #define	jadeMODE_RAC				0x40
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							|  |  |  | #define	jadeMODE_XAC				0x20
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							|  |  |  | #define	jadeMODE_TLP				0x10
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							|  |  |  | #define	jadeMODE_ERFS				0x02
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							|  |  |  | #define	jadeMODE_ETFS				0x01
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							|  |  |  | #define	jade_HDLC_RBCH					0x24				   /* R */
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										 |  |  | #define	jade_HDLC_RBCL					0x25				   /* R */
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							|  |  |  | #define	jade_HDLC_RCMD					0x25				   /* W */
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							|  |  |  | #define	jadeRCMD_RMC				0x80
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							|  |  |  | #define	jadeRCMD_RRES				0x40
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							|  |  |  | #define	jadeRCMD_RMD				0x20
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							|  |  |  | #define	jadeRCMD_STR				0x02
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							|  |  |  | #define	jade_HDLC_CCR0					0x26				   /* RW*/
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										 |  |  | #define	jadeCCR0_PU				0x80
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							|  |  |  | #define	jadeCCR0_ITF				0x40
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							|  |  |  | #define	jadeCCR0_C32				0x20
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							|  |  |  | #define	jadeCCR0_CRL				0x10
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							|  |  |  | #define	jadeCCR0_RCRC				0x08
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							|  |  |  | #define	jadeCCR0_XCRC				0x04
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							|  |  |  | #define	jadeCCR0_RMSB				0x02
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							|  |  |  | #define	jadeCCR0_XMSB				0x01
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							|  |  |  | #define	jade_HDLC_CCR1					0x27				   /* RW*/
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										 |  |  | #define	jadeCCR1_RCS0				0x80
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							|  |  |  | #define	jadeCCR1_RCONT				0x40
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							|  |  |  | #define	jadeCCR1_RFDIS				0x20
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							|  |  |  | #define	jadeCCR1_XCS0				0x10
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							|  |  |  | #define	jadeCCR1_XCONT				0x08
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							|  |  |  | #define	jadeCCR1_XFDIS				0x04
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							|  |  |  | #define	jade_HDLC_TSAR					0x28				   /* RW*/
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							|  |  |  | #define	jade_HDLC_TSAX					0x29				   /* RW*/
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							|  |  |  | #define	jade_HDLC_RCCR					0x2A				   /* RW*/
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							|  |  |  | #define	jade_HDLC_XCCR					0x2B				   /* RW*/
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										 |  |  | #define	jade_HDLC_ISR					0x2C				   /* R */
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							|  |  |  | #define	jade_HDLC_IMR					0x2C				   /* W */
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							|  |  |  | #define	jadeISR_RME					0x80
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							|  |  |  | #define	jadeISR_RPF					0x40
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							|  |  |  | #define	jadeISR_RFO					0x20
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							|  |  |  | #define	jadeISR_XPR					0x10
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							|  |  |  | #define	jadeISR_XDU					0x08
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							|  |  |  | #define	jadeISR_ALLS				0x04
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							|  |  |  | #define jade_INT				0x75
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							|  |  |  | #define jadeINT_HDLC1				0x02
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							|  |  |  | #define jadeINT_HDLC2				0x01
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							|  |  |  | #define jadeINT_DSP				0x04
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							|  |  |  | #define jade_INTR				0x70
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							|  |  |  | /********************************************************************/ | 
					
						
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										 |  |  | /* Indirect accessible JADE registers of common interest			*/ | 
					
						
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										 |  |  | /********************************************************************/ | 
					
						
							|  |  |  | #define	jade_CHIPVERSIONNR				0x00 /* Does not work*/
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										 |  |  | #define	jade_HDLCCNTRACCESS				0x10
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							|  |  |  | #define	jadeINDIRECT_HAH1			0x02
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							|  |  |  | #define	jadeINDIRECT_HAH2			0x01
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							|  |  |  | #define	jade_HDLC1SERRXPATH				0x1D
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							|  |  |  | #define	jade_HDLC1SERTXPATH				0x1E
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							|  |  |  | #define	jade_HDLC2SERRXPATH				0x1F
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							|  |  |  | #define	jade_HDLC2SERTXPATH				0x20
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										 |  |  | #define	jadeINDIRECT_SLIN1			0x10
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							|  |  |  | #define	jadeINDIRECT_SLIN0			0x08
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							|  |  |  | #define	jadeINDIRECT_LMOD1			0x04
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							|  |  |  | #define	jadeINDIRECT_LMOD0			0x02
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							|  |  |  | #define	jadeINDIRECT_HHR			0x01
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							|  |  |  | #define	jadeINDIRECT_HHX			0x01
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							|  |  |  | #define	jade_RXAUDIOCH1CFG				0x11
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							|  |  |  | #define	jade_RXAUDIOCH2CFG				0x14
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							|  |  |  | #define	jade_TXAUDIOCH1CFG				0x17
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							|  |  |  | #define	jade_TXAUDIOCH2CFG				0x1A
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							|  |  |  | extern int JadeVersion(struct IsdnCardState *cs, char *s); | 
					
						
							|  |  |  | extern void clear_pending_jade_ints(struct IsdnCardState *cs); | 
					
						
							|  |  |  | extern void initjade(struct IsdnCardState *cs); | 
					
						
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							|  |  |  | #endif	/* __JADE_H__ */
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