110 lines
3.8 KiB
C
110 lines
3.8 KiB
C
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#ifndef _GT64111_H_
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#define _GT64111_H_
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#define MASTER_INTERFACE 0x0
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#define RAS10_LO_DEC_ADR 0x8
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#define RAS10_HI_DEC_ADR 0x10
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#define RAS32_LO_DEC_ADR 0x18
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#define RAS32_HI_DEC_ADR 0x20
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#define CS20_LO_DEC_ADR 0x28
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#define CS20_HI_DEC_ADR 0x30
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#define CS3_LO_DEC_ADR 0x38
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#define CS3_HI_DEC_ADR 0x40
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#define PCI_IO_LO_DEC_ADR 0x48
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#define PCI_IO_HI_DEC_ADR 0x50
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#define PCI_MEM0_LO_DEC_ADR 0x58
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#define PCI_MEM0_HI_DEC_ADR 0x60
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#define INTERNAL_SPACE_DEC 0x68
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#define BUS_ERR_ADR_LO_CPU 0x70
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#define READONLY0 0x78
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#define PCI_MEM1_LO_DEC_ADR 0x80
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#define PCI_MEM1_HI_DEC_ADR 0x88
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#define RAS0_LO_DEC_ADR 0x400
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#define RAS0_HI_DEC_ADR 0x404
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#define RAS1_LO_DEC_ADR 0x408
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#define RAS1_HI_DEC_ADR 0x40c
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#define RAS2_LO_DEC_ADR 0x410
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#define RAS2_HI_DEC_ADR 0x414
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#define RAS3_LO_DEC_ADR 0x418
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#define RAS3_HI_DEC_ADR 0x41c
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#define DEV_CS0_LO_DEC_ADR 0x420
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#define DEV_CS0_HI_DEC_ADR 0x424
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#define DEV_CS1_LO_DEC_ADR 0x428
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#define DEV_CS1_HI_DEC_ADR 0x42c
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#define DEV_CS2_LO_DEC_ADR 0x430
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#define DEV_CS2_HI_DEC_ADR 0x434
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#define DEV_CS3_LO_DEC_ADR 0x438
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#define DEV_CS3_HI_DEC_ADR 0x43c
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#define DEV_BOOTCS_LO_DEC_ADR 0x440
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#define DEV_BOOTCS_HI_DEC_ADR 0x444
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#define DEV_ADR_DEC_ERR 0x470
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#define DRAM_CFG 0x448
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#define DRAM_BANK0_PARMS 0x44c
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#define DRAM_BANK1_PARMS 0x450
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#define DRAM_BANK2_PARMS 0x454
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#define DRAM_BANK3_PARMS 0x458
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#define DEV_BANK0_PARMS 0x45c
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#define DEV_BANK1_PARMS 0x460
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#define DEV_BANK2_PARMS 0x464
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#define DEV_BANK3_PARMS 0x468
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#define DEV_BOOT_BANK_PARMS 0x46c
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#define CH0_DMA_BYTECOUNT 0x800
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#define CH1_DMA_BYTECOUNT 0x804
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#define CH2_DMA_BYTECOUNT 0x808
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#define CH3_DMA_BYTECOUNT 0x80c
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#define CH0_DMA_SRC_ADR 0x810
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#define CH1_DMA_SRC_ADR 0x814
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#define CH2_DMA_SRC_ADR 0x818
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#define CH3_DMA_SRC_ADR 0x81c
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#define CH0_DMA_DST_ADR 0x820
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#define CH1_DMA_DST_ADR 0x824
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#define CH2_DMA_DST_ADR 0x828
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#define CH3_DMA_DST_ADR 0x82c
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#define CH0_NEXT_REC_PTR 0x830
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#define CH1_NEXT_REC_PTR 0x834
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#define CH2_NEXT_REC_PTR 0x838
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#define CH3_NEXT_REC_PTR 0x83c
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#define CH0_CTRL 0x840
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#define CH1_CTRL 0x844
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#define CH2_CTRL 0x848
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#define CH3_CTRL 0x84c
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#define DMA_ARBITER 0x860
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#define TIMER0 0x850
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#define TIMER1 0x854
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#define TIMER2 0x858
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#define TIMER3 0x85c
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#define TIMER_CTRL 0x864
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#define PCI_CMD 0xc00
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#define PCI_TIMEOUT 0xc04
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#define PCI_RAS10_BANK_SIZE 0xc08
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#define PCI_RAS32_BANK_SIZE 0xc0c
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#define PCI_CS20_BANK_SIZE 0xc10
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#define PCI_CS3_BANK_SIZE 0xc14
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#define PCI_SERRMASK 0xc28
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#define PCI_INTACK 0xc34
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#define PCI_BAR_EN 0xc3c
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#define PCI_CFG_ADR 0xcf8
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#define PCI_CFG_DATA 0xcfc
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#define PCI_INTCAUSE 0xc18
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#define PCI_MAST_MASK 0xc1c
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#define PCI_PCIMASK 0xc24
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#define BAR_ENABLE_ADR 0xc3c
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/* These are config registers, accessible via PCI space */
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#define PCI_CONFIG_RAS10_BASE_ADR 0x010
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#define PCI_CONFIG_RAS32_BASE_ADR 0x014
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#define PCI_CONFIG_CS20_BASE_ADR 0x018
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#define PCI_CONFIG_CS3_BASE_ADR 0x01c
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#define PCI_CONFIG_INT_REG_MM_ADR 0x020
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#define PCI_CONFIG_INT_REG_IO_ADR 0x024
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#define PCI_CONFIG_BOARD_VENDOR 0x02c
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#define PCI_CONFIG_ROM_ADR 0x030
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#define PCI_CONFIG_INT_PIN_LINE 0x03c
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#endif
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