39 lines
		
	
	
	
		
			914 B
			
		
	
	
	
		
			C
		
	
	
	
	
	
		
		
			
		
	
	
			39 lines
		
	
	
	
		
			914 B
			
		
	
	
	
		
			C
		
	
	
	
	
	
|   | #ifndef _ASM_POWERPC_CACHE_H
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|  | #define _ASM_POWERPC_CACHE_H
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|  | 
 | ||
|  | #ifdef __KERNEL__
 | ||
|  | 
 | ||
|  | 
 | ||
|  | /* bytes per L1 cache line */ | ||
|  | #if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
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|  | #define L1_CACHE_SHIFT		4
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|  | #define MAX_COPY_PREFETCH	1
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|  | #elif defined(CONFIG_PPC32)
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|  | #define L1_CACHE_SHIFT		5
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|  | #define MAX_COPY_PREFETCH	4
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|  | #else /* CONFIG_PPC64 */
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|  | #define L1_CACHE_SHIFT		7
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|  | #endif
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|  | 
 | ||
|  | #define	L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
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|  | 
 | ||
|  | #define	SMP_CACHE_BYTES		L1_CACHE_BYTES
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|  | 
 | ||
|  | #if defined(__powerpc64__) && !defined(__ASSEMBLY__)
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|  | struct ppc64_caches { | ||
|  | 	u32	dsize;			/* L1 d-cache size */ | ||
|  | 	u32	dline_size;		/* L1 d-cache line size	*/ | ||
|  | 	u32	log_dline_size; | ||
|  | 	u32	dlines_per_page; | ||
|  | 	u32	isize;			/* L1 i-cache size */ | ||
|  | 	u32	iline_size;		/* L1 i-cache line size	*/ | ||
|  | 	u32	log_iline_size; | ||
|  | 	u32	ilines_per_page; | ||
|  | }; | ||
|  | 
 | ||
|  | extern struct ppc64_caches ppc64_caches; | ||
|  | #endif /* __powerpc64__ && ! __ASSEMBLY__ */
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|  | 
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|  | #endif /* __KERNEL__ */
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|  | #endif /* _ASM_POWERPC_CACHE_H */
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