368 lines
10 KiB
C
368 lines
10 KiB
C
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/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/ioport.h>
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#include <linux/export.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <lantiq_soc.h>
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#include "../clk.h"
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#include "../prom.h"
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/* clock control register */
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#define CGU_IFCCR 0x0018
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/* system clock register */
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#define CGU_SYS 0x0010
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/* pci control register */
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#define CGU_PCICR 0x0034
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/* ephy configuration register */
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#define CGU_EPHY 0x10
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/* power control register */
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#define PMU_PWDCR 0x1C
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/* power status register */
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#define PMU_PWDSR 0x20
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/* power control register */
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#define PMU_PWDCR1 0x24
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/* power status register */
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#define PMU_PWDSR1 0x28
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/* power control register */
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#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
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/* power status register */
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#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
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/* clock gates that we can en/disable */
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#define PMU_USB0_P BIT(0)
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#define PMU_PCI BIT(4)
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#define PMU_USB0 BIT(6)
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#define PMU_ASC0 BIT(7)
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#define PMU_EPHY BIT(7) /* ase */
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#define PMU_SPI BIT(8)
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#define PMU_DFE BIT(9)
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#define PMU_EBU BIT(10)
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#define PMU_STP BIT(11)
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#define PMU_AHBS BIT(13) /* vr9 */
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#define PMU_AHBM BIT(15)
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#define PMU_ASC1 BIT(17)
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#define PMU_PPE_QSB BIT(18)
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#define PMU_PPE_SLL01 BIT(19)
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#define PMU_PPE_TC BIT(21)
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#define PMU_PPE_EMA BIT(22)
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#define PMU_PPE_DPLUM BIT(23)
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#define PMU_PPE_DPLUS BIT(24)
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#define PMU_USB1_P BIT(26)
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#define PMU_USB1 BIT(27)
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#define PMU_PPE_TOP BIT(29)
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#define PMU_GPHY BIT(30)
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#define PMU_PCIE_CLK BIT(31)
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#define PMU1_PCIE_PHY BIT(0)
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#define PMU1_PCIE_CTL BIT(1)
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#define PMU1_PCIE_PDI BIT(4)
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#define PMU1_PCIE_MSI BIT(5)
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#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
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#define pmu_r32(x) ltq_r32(pmu_membase + (x))
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static void __iomem *pmu_membase;
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void __iomem *ltq_cgu_membase;
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void __iomem *ltq_ebu_membase;
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/* legacy function kept alive to ease clkdev transition */
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void ltq_pmu_enable(unsigned int module)
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{
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int err = 1000000;
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pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
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do {} while (--err && (pmu_r32(PMU_PWDSR) & module));
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if (!err)
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panic("activating PMU module failed!");
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}
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EXPORT_SYMBOL(ltq_pmu_enable);
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/* legacy function kept alive to ease clkdev transition */
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void ltq_pmu_disable(unsigned int module)
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{
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pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
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}
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EXPORT_SYMBOL(ltq_pmu_disable);
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/* enable a hw clock */
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static int cgu_enable(struct clk *clk)
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{
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ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
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return 0;
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}
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/* disable a hw clock */
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static void cgu_disable(struct clk *clk)
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{
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ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
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}
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/* enable a clock gate */
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static int pmu_enable(struct clk *clk)
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{
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int retry = 1000000;
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pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
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PWDCR(clk->module));
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do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
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if (!retry)
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panic("activating PMU module failed!\n");
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return 0;
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}
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/* disable a clock gate */
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static void pmu_disable(struct clk *clk)
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{
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pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
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PWDCR(clk->module));
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}
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/* the pci enable helper */
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static int pci_enable(struct clk *clk)
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{
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unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
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/* set bus clock speed */
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if (of_machine_is_compatible("lantiq,ar9")) {
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ifccr &= ~0x1f00000;
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if (clk->rate == CLOCK_33M)
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ifccr |= 0xe00000;
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else
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ifccr |= 0x700000; /* 62.5M */
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} else {
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ifccr &= ~0xf00000;
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if (clk->rate == CLOCK_33M)
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ifccr |= 0x800000;
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else
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ifccr |= 0x400000; /* 62.5M */
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}
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ltq_cgu_w32(ifccr, CGU_IFCCR);
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pmu_enable(clk);
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return 0;
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}
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/* enable the external clock as a source */
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static int pci_ext_enable(struct clk *clk)
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{
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ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
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CGU_IFCCR);
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ltq_cgu_w32((1 << 30), CGU_PCICR);
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return 0;
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}
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/* disable the external clock as a source */
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static void pci_ext_disable(struct clk *clk)
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{
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ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
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CGU_IFCCR);
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ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
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}
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/* enable a clockout source */
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static int clkout_enable(struct clk *clk)
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{
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int i;
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/* get the correct rate */
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for (i = 0; i < 4; i++) {
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if (clk->rates[i] == clk->rate) {
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int shift = 14 - (2 * clk->module);
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unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
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ifccr &= ~(3 << shift);
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ifccr |= i << shift;
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ltq_cgu_w32(ifccr, CGU_IFCCR);
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return 0;
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}
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}
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return -1;
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}
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/* manage the clock gates via PMU */
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static void clkdev_add_pmu(const char *dev, const char *con,
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unsigned int module, unsigned int bits)
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{
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struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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clk->cl.dev_id = dev;
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clk->cl.con_id = con;
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clk->cl.clk = clk;
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clk->enable = pmu_enable;
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clk->disable = pmu_disable;
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clk->module = module;
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clk->bits = bits;
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clkdev_add(&clk->cl);
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}
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/* manage the clock generator */
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static void clkdev_add_cgu(const char *dev, const char *con,
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unsigned int bits)
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{
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struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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clk->cl.dev_id = dev;
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clk->cl.con_id = con;
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clk->cl.clk = clk;
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clk->enable = cgu_enable;
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clk->disable = cgu_disable;
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clk->bits = bits;
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clkdev_add(&clk->cl);
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}
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/* pci needs its own enable function as the setup is a bit more complex */
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static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
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static void clkdev_add_pci(void)
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{
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struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
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/* main pci clock */
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clk->cl.dev_id = "17000000.pci";
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clk->cl.con_id = NULL;
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clk->cl.clk = clk;
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clk->rate = CLOCK_33M;
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clk->rates = valid_pci_rates;
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clk->enable = pci_enable;
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clk->disable = pmu_disable;
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clk->module = 0;
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clk->bits = PMU_PCI;
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clkdev_add(&clk->cl);
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/* use internal/external bus clock */
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clk_ext->cl.dev_id = "17000000.pci";
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clk_ext->cl.con_id = "external";
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clk_ext->cl.clk = clk_ext;
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clk_ext->enable = pci_ext_enable;
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clk_ext->disable = pci_ext_disable;
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clkdev_add(&clk_ext->cl);
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}
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/* xway socs can generate clocks on gpio pins */
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static unsigned long valid_clkout_rates[4][5] = {
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{CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
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{CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
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{CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
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{CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
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};
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static void clkdev_add_clkout(void)
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{
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int i;
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for (i = 0; i < 4; i++) {
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struct clk *clk;
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char *name;
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name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
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sprintf(name, "clkout%d", i);
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clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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clk->cl.dev_id = "1f103000.cgu";
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clk->cl.con_id = name;
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clk->cl.clk = clk;
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clk->rate = 0;
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clk->rates = valid_clkout_rates[i];
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clk->enable = clkout_enable;
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clk->module = i;
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clkdev_add(&clk->cl);
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}
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}
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/* bring up all register ranges that we need for basic system control */
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void __init ltq_soc_init(void)
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{
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struct resource res_pmu, res_cgu, res_ebu;
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struct device_node *np_pmu =
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of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
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struct device_node *np_cgu =
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of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
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struct device_node *np_ebu =
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of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
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/* check if all the core register ranges are available */
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if (!np_pmu || !np_cgu || !np_ebu)
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panic("Failed to load core nodess from devicetree");
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if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
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of_address_to_resource(np_cgu, 0, &res_cgu) ||
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of_address_to_resource(np_ebu, 0, &res_ebu))
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panic("Failed to get core resources");
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if ((request_mem_region(res_pmu.start, resource_size(&res_pmu),
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res_pmu.name) < 0) ||
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(request_mem_region(res_cgu.start, resource_size(&res_cgu),
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res_cgu.name) < 0) ||
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(request_mem_region(res_ebu.start, resource_size(&res_ebu),
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res_ebu.name) < 0))
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pr_err("Failed to request core reources");
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pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
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ltq_cgu_membase = ioremap_nocache(res_cgu.start,
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resource_size(&res_cgu));
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ltq_ebu_membase = ioremap_nocache(res_ebu.start,
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resource_size(&res_ebu));
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if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
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panic("Failed to remap core resources");
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/* make sure to unprotect the memory region where flash is located */
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
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/* add our generic xway clocks */
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clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI);
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clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0);
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clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT);
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clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP);
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clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA);
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clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI);
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clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU);
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clkdev_add_clkout();
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/* add the soc dependent clocks */
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if (!of_machine_is_compatible("lantiq,vr9"))
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clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
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if (!of_machine_is_compatible("lantiq,ase")) {
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clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
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clkdev_add_pci();
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}
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if (of_machine_is_compatible("lantiq,ase")) {
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if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
|
||
|
|
clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
|
||
|
|
else
|
||
|
|
clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
|
||
|
|
clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
|
||
|
|
clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
|
||
|
|
} else if (of_machine_is_compatible("lantiq,vr9")) {
|
||
|
|
clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
|
||
|
|
ltq_vr9_fpi_hz());
|
||
|
|
clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
|
||
|
|
clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
|
||
|
|
clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
|
||
|
|
clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
|
||
|
|
clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
|
||
|
|
clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
|
||
|
|
} else if (of_machine_is_compatible("lantiq,ar9")) {
|
||
|
|
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
|
||
|
|
ltq_ar9_fpi_hz());
|
||
|
|
clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
|
||
|
|
} else {
|
||
|
|
clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
|
||
|
|
ltq_danube_fpi_hz());
|
||
|
|
}
|
||
|
|
}
|