2014-06-12 18:36:37 +03:00
										 
									 
								 
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								/*
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								 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
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								 *
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								 * This program is free software; you can redistribute it and/or modify it
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								 * under the terms and conditions of the GNU General Public License,
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								 * version 2, as published by the Free Software Foundation.
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								 *
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								 * This program is distributed in the hope it will be useful, but WITHOUT
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								 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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								 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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								 * more details.
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								 *
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								 * You should have received a copy of the GNU General Public License
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								 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
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								 *
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								 */
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								#include <linux/kernel.h>
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								#include <linux/of.h>
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								#include <linux/of_address.h>
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								#include <linux/io.h>
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								#include <soc/tegra/fuse.h>
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								#include "fuse.h"
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								#define APBMISC_BASE	0x70000800
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								#define APBMISC_SIZE	0x64
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								#define FUSE_SKU_INFO	0x10
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								static void __iomem *apbmisc_base;
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								static void __iomem *strapping_base;
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								u32 tegra_read_chipid(void)
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								{
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									return readl_relaxed(apbmisc_base + 4);
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								}
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								u8 tegra_get_chip_id(void)
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								{
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									if (!apbmisc_base) {
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										WARN(1, "Tegra Chip ID not yet available\n");
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										return 0;
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									}
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											2014-07-11 11:13:30 +02:00
										 
									 
								 
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									return (tegra_read_chipid() >> 8) & 0xff;
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											2014-06-12 18:36:37 +03:00
										 
									 
								 
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								}
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								u32 tegra_read_straps(void)
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								{
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									if (strapping_base)
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										return readl_relaxed(strapping_base);
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									else
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										return 0;
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								}
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								static const struct of_device_id apbmisc_match[] __initconst = {
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									{ .compatible = "nvidia,tegra20-apbmisc", },
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									{},
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								};
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								void __init tegra_init_revision(void)
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								{
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									u32 id, chip_id, minor_rev;
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									int rev;
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									id = tegra_read_chipid();
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									chip_id = (id >> 8) & 0xff;
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									minor_rev = (id >> 16) & 0xf;
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									switch (minor_rev) {
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									case 1:
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										rev = TEGRA_REVISION_A01;
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										break;
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									case 2:
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										rev = TEGRA_REVISION_A02;
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										break;
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									case 3:
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										if (chip_id == TEGRA20 && (tegra20_spare_fuse_early(18) ||
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													   tegra20_spare_fuse_early(19)))
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											rev = TEGRA_REVISION_A03p;
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										else
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											rev = TEGRA_REVISION_A03;
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										break;
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									case 4:
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										rev = TEGRA_REVISION_A04;
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										break;
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									default:
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										rev = TEGRA_REVISION_UNKNOWN;
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									}
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									tegra_sku_info.revision = rev;
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									if (chip_id == TEGRA20)
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										tegra_sku_info.sku_id = tegra20_fuse_early(FUSE_SKU_INFO);
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									else
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										tegra_sku_info.sku_id = tegra30_fuse_readl(FUSE_SKU_INFO);
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								}
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								void __init tegra_init_apbmisc(void)
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								{
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									struct device_node *np;
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									np = of_find_matching_node(NULL, apbmisc_match);
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									apbmisc_base = of_iomap(np, 0);
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									if (!apbmisc_base) {
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										pr_warn("ioremap tegra apbmisc failed. using %08x instead\n",
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											APBMISC_BASE);
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										apbmisc_base = ioremap(APBMISC_BASE, APBMISC_SIZE);
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									}
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									strapping_base = of_iomap(np, 1);
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									if (!strapping_base)
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										pr_err("ioremap tegra strapping_base failed\n");
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								}
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