2013-11-05 23:11:51 +10:00
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/*
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* imx50 pinctrl driver based on imx pinmux core
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*
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* Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2012 Linaro, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-imx.h"
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enum imx50_pads {
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MX50_PAD_RESERVE0 = 0,
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MX50_PAD_RESERVE1 = 1,
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MX50_PAD_RESERVE2 = 2,
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MX50_PAD_RESERVE3 = 3,
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MX50_PAD_RESERVE4 = 4,
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MX50_PAD_RESERVE5 = 5,
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MX50_PAD_RESERVE6 = 6,
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MX50_PAD_RESERVE7 = 7,
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MX50_PAD_KEY_COL0 = 8,
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MX50_PAD_KEY_ROW0 = 9,
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MX50_PAD_KEY_COL1 = 10,
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MX50_PAD_KEY_ROW1 = 11,
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MX50_PAD_KEY_COL2 = 12,
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MX50_PAD_KEY_ROW2 = 13,
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MX50_PAD_KEY_COL3 = 14,
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MX50_PAD_KEY_ROW3 = 15,
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MX50_PAD_I2C1_SCL = 16,
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MX50_PAD_I2C1_SDA = 17,
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MX50_PAD_I2C2_SCL = 18,
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MX50_PAD_I2C2_SDA = 19,
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MX50_PAD_I2C3_SCL = 20,
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MX50_PAD_I2C3_SDA = 21,
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MX50_PAD_PWM1 = 22,
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MX50_PAD_PWM2 = 23,
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MX50_PAD_0WIRE = 24,
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MX50_PAD_EPITO = 25,
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MX50_PAD_WDOG = 26,
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MX50_PAD_SSI_TXFS = 27,
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MX50_PAD_SSI_TXC = 28,
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MX50_PAD_SSI_TXD = 29,
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MX50_PAD_SSI_RXD = 30,
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MX50_PAD_SSI_RXF = 31,
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MX50_PAD_SSI_RXC = 32,
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MX50_PAD_UART1_TXD = 33,
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MX50_PAD_UART1_RXD = 34,
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MX50_PAD_UART1_CTS = 35,
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MX50_PAD_UART1_RTS = 36,
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MX50_PAD_UART2_TXD = 37,
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MX50_PAD_UART2_RXD = 38,
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MX50_PAD_UART2_CTS = 39,
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MX50_PAD_UART2_RTS = 40,
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MX50_PAD_UART3_TXD = 41,
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MX50_PAD_UART3_RXD = 42,
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MX50_PAD_UART4_TXD = 43,
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MX50_PAD_UART4_RXD = 44,
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MX50_PAD_CSPI_CLK = 45,
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MX50_PAD_CSPI_MOSI = 46,
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MX50_PAD_CSPI_MISO = 47,
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MX50_PAD_CSPI_SS0 = 48,
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MX50_PAD_ECSPI1_CLK = 49,
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MX50_PAD_ECSPI1_MOSI = 50,
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MX50_PAD_ECSPI1_MISO = 51,
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MX50_PAD_ECSPI1_SS0 = 52,
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MX50_PAD_ECSPI2_CLK = 53,
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MX50_PAD_ECSPI2_MOSI = 54,
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MX50_PAD_ECSPI2_MISO = 55,
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MX50_PAD_ECSPI2_SS0 = 56,
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MX50_PAD_SD1_CLK = 57,
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MX50_PAD_SD1_CMD = 58,
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MX50_PAD_SD1_D0 = 59,
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MX50_PAD_SD1_D1 = 60,
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MX50_PAD_SD1_D2 = 61,
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MX50_PAD_SD1_D3 = 62,
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MX50_PAD_SD2_CLK = 63,
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MX50_PAD_SD2_CMD = 64,
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MX50_PAD_SD2_D0 = 65,
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MX50_PAD_SD2_D1 = 66,
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MX50_PAD_SD2_D2 = 67,
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MX50_PAD_SD2_D3 = 68,
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MX50_PAD_SD2_D4 = 69,
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MX50_PAD_SD2_D5 = 70,
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MX50_PAD_SD2_D6 = 71,
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MX50_PAD_SD2_D7 = 72,
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MX50_PAD_SD2_WP = 73,
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MX50_PAD_SD2_CD = 74,
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MX50_PAD_DISP_D0 = 75,
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MX50_PAD_DISP_D1 = 76,
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MX50_PAD_DISP_D2 = 77,
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MX50_PAD_DISP_D3 = 78,
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MX50_PAD_DISP_D4 = 79,
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MX50_PAD_DISP_D5 = 80,
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MX50_PAD_DISP_D6 = 81,
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MX50_PAD_DISP_D7 = 82,
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MX50_PAD_DISP_WR = 83,
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MX50_PAD_DISP_RD = 84,
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MX50_PAD_DISP_RS = 85,
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MX50_PAD_DISP_CS = 86,
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MX50_PAD_DISP_BUSY = 87,
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MX50_PAD_DISP_RESET = 88,
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MX50_PAD_SD3_CLK = 89,
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MX50_PAD_SD3_CMD = 90,
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MX50_PAD_SD3_D0 = 91,
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MX50_PAD_SD3_D1 = 92,
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MX50_PAD_SD3_D2 = 93,
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MX50_PAD_SD3_D3 = 94,
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MX50_PAD_SD3_D4 = 95,
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MX50_PAD_SD3_D5 = 96,
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MX50_PAD_SD3_D6 = 97,
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MX50_PAD_SD3_D7 = 98,
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MX50_PAD_SD3_WP = 99,
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MX50_PAD_DISP_D8 = 100,
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MX50_PAD_DISP_D9 = 101,
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MX50_PAD_DISP_D10 = 102,
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MX50_PAD_DISP_D11 = 103,
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MX50_PAD_DISP_D12 = 104,
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MX50_PAD_DISP_D13 = 105,
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MX50_PAD_DISP_D14 = 106,
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MX50_PAD_DISP_D15 = 107,
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MX50_PAD_EPDC_D0 = 108,
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MX50_PAD_EPDC_D1 = 109,
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MX50_PAD_EPDC_D2 = 110,
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MX50_PAD_EPDC_D3 = 111,
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MX50_PAD_EPDC_D4 = 112,
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MX50_PAD_EPDC_D5 = 113,
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MX50_PAD_EPDC_D6 = 114,
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MX50_PAD_EPDC_D7 = 115,
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MX50_PAD_EPDC_D8 = 116,
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MX50_PAD_EPDC_D9 = 117,
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MX50_PAD_EPDC_D10 = 118,
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MX50_PAD_EPDC_D11 = 119,
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MX50_PAD_EPDC_D12 = 120,
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MX50_PAD_EPDC_D13 = 121,
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MX50_PAD_EPDC_D14 = 122,
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MX50_PAD_EPDC_D15 = 123,
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MX50_PAD_EPDC_GDCLK = 124,
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MX50_PAD_EPDC_GDSP = 125,
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MX50_PAD_EPDC_GDOE = 126,
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MX50_PAD_EPDC_GDRL = 127,
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MX50_PAD_EPDC_SDCLK = 128,
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MX50_PAD_EPDC_SDOEZ = 129,
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MX50_PAD_EPDC_SDOED = 130,
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MX50_PAD_EPDC_SDOE = 131,
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MX50_PAD_EPDC_SDLE = 132,
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MX50_PAD_EPDC_SDCLKN = 133,
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MX50_PAD_EPDC_SDSHR = 134,
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MX50_PAD_EPDC_PWRCOM = 135,
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MX50_PAD_EPDC_PWRSTAT = 136,
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MX50_PAD_EPDC_PWRCTRL0 = 137,
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MX50_PAD_EPDC_PWRCTRL1 = 138,
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MX50_PAD_EPDC_PWRCTRL2 = 139,
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MX50_PAD_EPDC_PWRCTRL3 = 140,
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MX50_PAD_EPDC_VCOM0 = 141,
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MX50_PAD_EPDC_VCOM1 = 142,
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MX50_PAD_EPDC_BDR0 = 143,
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MX50_PAD_EPDC_BDR1 = 144,
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MX50_PAD_EPDC_SDCE0 = 145,
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MX50_PAD_EPDC_SDCE1 = 146,
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MX50_PAD_EPDC_SDCE2 = 147,
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MX50_PAD_EPDC_SDCE3 = 148,
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MX50_PAD_EPDC_SDCE4 = 149,
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MX50_PAD_EPDC_SDCE5 = 150,
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MX50_PAD_EIM_DA0 = 151,
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MX50_PAD_EIM_DA1 = 152,
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MX50_PAD_EIM_DA2 = 153,
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MX50_PAD_EIM_DA3 = 154,
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MX50_PAD_EIM_DA4 = 155,
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MX50_PAD_EIM_DA5 = 156,
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MX50_PAD_EIM_DA6 = 157,
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MX50_PAD_EIM_DA7 = 158,
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MX50_PAD_EIM_DA8 = 159,
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MX50_PAD_EIM_DA9 = 160,
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MX50_PAD_EIM_DA10 = 161,
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MX50_PAD_EIM_DA11 = 162,
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MX50_PAD_EIM_DA12 = 163,
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MX50_PAD_EIM_DA13 = 164,
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MX50_PAD_EIM_DA14 = 165,
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MX50_PAD_EIM_DA15 = 166,
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MX50_PAD_EIM_CS2 = 167,
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MX50_PAD_EIM_CS1 = 168,
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MX50_PAD_EIM_CS0 = 169,
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MX50_PAD_EIM_EB0 = 170,
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MX50_PAD_EIM_EB1 = 171,
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MX50_PAD_EIM_WAIT = 172,
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MX50_PAD_EIM_BCLK = 173,
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MX50_PAD_EIM_RDY = 174,
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MX50_PAD_EIM_OE = 175,
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MX50_PAD_EIM_RW = 176,
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MX50_PAD_EIM_LBA = 177,
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MX50_PAD_EIM_CRE = 178,
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};
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/* Pad names for the pinmux subsystem */
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static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
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IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
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IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
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IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
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IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
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IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
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IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
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IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
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IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
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IMX_PINCTRL_PIN(MX50_PAD_PWM1),
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IMX_PINCTRL_PIN(MX50_PAD_PWM2),
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IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
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IMX_PINCTRL_PIN(MX50_PAD_EPITO),
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IMX_PINCTRL_PIN(MX50_PAD_WDOG),
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IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
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IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
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IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
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IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
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IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
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IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
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IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
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IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
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IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
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IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
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IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
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IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
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IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
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IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
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IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
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IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
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IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
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IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
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IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
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IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
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IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
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IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
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IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
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IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
|
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
|
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|
|
|
IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
|
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
|
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|
|
|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
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|
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
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|
IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
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IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
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|
IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
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IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
|
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
|
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|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
|
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
|
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IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
|
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|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
|
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|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
|
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
|
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|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
|
|
|
|
|
IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
|
|
|
|
|
.pins = imx50_pinctrl_pads,
|
|
|
|
|
.npins = ARRAY_SIZE(imx50_pinctrl_pads),
|
|
|
|
|
};
|
|
|
|
|
|
2014-08-11 16:47:50 +05:30
|
|
|
static const struct of_device_id imx50_pinctrl_of_match[] = {
|
2013-11-05 23:11:51 +10:00
|
|
|
{ .compatible = "fsl,imx50-iomuxc", },
|
|
|
|
|
{ /* sentinel */ }
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int imx50_pinctrl_probe(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static struct platform_driver imx50_pinctrl_driver = {
|
|
|
|
|
.driver = {
|
|
|
|
|
.name = "imx50-pinctrl",
|
|
|
|
|
.of_match_table = of_match_ptr(imx50_pinctrl_of_match),
|
|
|
|
|
},
|
|
|
|
|
.probe = imx50_pinctrl_probe,
|
|
|
|
|
.remove = imx_pinctrl_remove,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static int __init imx50_pinctrl_init(void)
|
|
|
|
|
{
|
|
|
|
|
return platform_driver_register(&imx50_pinctrl_driver);
|
|
|
|
|
}
|
|
|
|
|
arch_initcall(imx50_pinctrl_init);
|
|
|
|
|
|
|
|
|
|
static void __exit imx50_pinctrl_exit(void)
|
|
|
|
|
{
|
|
|
|
|
platform_driver_unregister(&imx50_pinctrl_driver);
|
|
|
|
|
}
|
|
|
|
|
module_exit(imx50_pinctrl_exit);
|
|
|
|
|
MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
|
|
|
|
|
MODULE_LICENSE("GPL v2");
|
