linux-pinenote/arch/arm/mach-iop13xx/include/mach/uncompress.h

#include <asm/types.h>
#include <linux/serial_reg.h>
#include <mach/hardware.h>

#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)

static inline void putc(char c)
{
	while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
		barrier();
	UART_BASE[UART_TX] = c;
}

static inline void flush(void)
{
}

/*
 * nothing to do
 */
#define arch_decomp_setup()
[ARM] 3995/1: iop13xx: add iop13xx support The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2006-12-07 02:59:39 +01:00			`#include <asm/types.h>`
			`#include <linux/serial_reg.h>`
[ARM] Move include/asm-arm/arch-* to arch/arm//include/mach This just leaves include/asm-arm/plat- to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2008-08-05 16:14:15 +01:00			`#include <mach/hardware.h>`
[ARM] 3995/1: iop13xx: add iop13xx support The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2006-12-07 02:59:39 +01:00
			`#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)`
			`#define TX_DONE (UART_LSR_TEMT \| UART_LSR_THRE)`

			`static inline void putc(char c)`
			`{`
			`while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)`
[ARM] 4494/1: iop13xx: fix up elf_hwcap compile breakage arch/arm/boot/compressed/misc.o: In function `valid_user_regs': misc.c:(.text+0x74): undefined reference to `elf_hwcap' This triggers after the various elf_hwcap cleanups in: f884b1cf578e079f01682514ae1ae64c74586602 d1cbbd6b413510c6512f4f80ffd48db1a8dd554a include/asm-arm/arch-iop13xx/uncompress.h calls cpu_relax while spinning on a register value. cpu_relax requires processor.h->ptrace.h->hwcap.h 'elf_hwcap' is defined as an extern, but since the uncompressor does not link against arch/arm/kernel/setup.c 'elf_hwcap' remains undefined. Fix is to open code the cpu_relax() call as barrier(). Cc: Lennert Buytenhek <kernel@wantstofly.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2007-07-20 02:07:31 +01:00			`barrier();`
[ARM] 3995/1: iop13xx: add iop13xx support The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 2006-12-07 02:59:39 +01:00			`UART_BASE[UART_TX] = c;`
			`}`

			`static inline void flush(void)`
			`{`
			`}`

			`/*`
			`* nothing to do`
			`*/`
			`#define arch_decomp_setup()`