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										 |  |  | /*
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							|  |  |  |  * arch/arm/mach-dove/include/mach/dove.h | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Generic definitions for Marvell Dove 88AP510 SoC | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This file is licensed under the terms of the GNU General Public | 
					
						
							|  |  |  |  * License version 2.  This program is licensed "as is" without any | 
					
						
							|  |  |  |  * warranty of any kind, whether express or implied. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
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							|  |  |  | #ifndef __ASM_ARCH_DOVE_H
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							|  |  |  | #define __ASM_ARCH_DOVE_H
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							|  |  |  | 
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							|  |  |  | /*
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							|  |  |  |  * Marvell Dove address maps. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * phys		virt		size | 
					
						
							|  |  |  |  * c8000000	fdb00000	1M	Cryptographic SRAM | 
					
						
							|  |  |  |  * e0000000	@runtime	128M	PCIe-0 Memory space | 
					
						
							|  |  |  |  * e8000000	@runtime	128M	PCIe-1 Memory space | 
					
						
							|  |  |  |  * f1000000	fde00000	8M	on-chip south-bridge registers | 
					
						
							|  |  |  |  * f1800000	fe600000	8M	on-chip north-bridge registers | 
					
						
							|  |  |  |  * f2000000	fee00000	1M	PCIe-0 I/O space | 
					
						
							|  |  |  |  * f2100000	fef00000	1M	PCIe-1 I/O space | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
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							|  |  |  | #define DOVE_CESA_PHYS_BASE		0xc8000000
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										 |  |  | #define DOVE_CESA_VIRT_BASE		IOMEM(0xfdb00000)
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										 |  |  | #define DOVE_CESA_SIZE			SZ_1M
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							|  |  |  | 
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							|  |  |  | #define DOVE_PCIE0_MEM_PHYS_BASE	0xe0000000
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							|  |  |  | #define DOVE_PCIE0_MEM_SIZE		SZ_128M
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							|  |  |  | 
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							|  |  |  | #define DOVE_PCIE1_MEM_PHYS_BASE	0xe8000000
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							|  |  |  | #define DOVE_PCIE1_MEM_SIZE		SZ_128M
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							|  |  |  | 
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							|  |  |  | #define DOVE_BOOTROM_PHYS_BASE		0xf8000000
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							|  |  |  | #define DOVE_BOOTROM_SIZE		SZ_128M
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							|  |  |  | 
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							|  |  |  | #define DOVE_SCRATCHPAD_PHYS_BASE	0xf0000000
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										 |  |  | #define DOVE_SCRATCHPAD_VIRT_BASE	IOMEM(0xfdd00000)
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										 |  |  | #define DOVE_SCRATCHPAD_SIZE		SZ_1M
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							|  |  |  | 
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							|  |  |  | #define DOVE_SB_REGS_PHYS_BASE		0xf1000000
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										 |  |  | #define DOVE_SB_REGS_VIRT_BASE		IOMEM(0xfde00000)
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										 |  |  | #define DOVE_SB_REGS_SIZE		SZ_8M
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							|  |  |  | 
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							|  |  |  | #define DOVE_NB_REGS_PHYS_BASE		0xf1800000
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										 |  |  | #define DOVE_NB_REGS_VIRT_BASE		IOMEM(0xfe600000)
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										 |  |  | #define DOVE_NB_REGS_SIZE		SZ_8M
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							|  |  |  | 
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							|  |  |  | #define DOVE_PCIE0_IO_PHYS_BASE		0xf2000000
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							|  |  |  | #define DOVE_PCIE0_IO_BUS_BASE		0x00000000
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										 |  |  | #define DOVE_PCIE0_IO_SIZE		SZ_64K
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							|  |  |  | #define DOVE_PCIE1_IO_PHYS_BASE		0xf2100000
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										 |  |  | #define DOVE_PCIE1_IO_BUS_BASE		0x00010000
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							|  |  |  | #define DOVE_PCIE1_IO_SIZE		SZ_64K
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							|  |  |  | /*
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							|  |  |  |  * Dove Core Registers Map | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | 
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							|  |  |  | /* SPI, I2C, UART */ | 
					
						
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										 |  |  | #define DOVE_I2C_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x11000)
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							|  |  |  | #define DOVE_UART0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12000)
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							|  |  |  | #define DOVE_UART0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12000)
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							|  |  |  | #define DOVE_UART1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12100)
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							|  |  |  | #define DOVE_UART1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12100)
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							|  |  |  | #define DOVE_UART2_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12200)
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							|  |  |  | #define DOVE_UART2_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12200)
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							|  |  |  | #define DOVE_UART3_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x12300)
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							|  |  |  | #define DOVE_UART3_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x12300)
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							|  |  |  | #define DOVE_SPI0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x10600)
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							|  |  |  | #define DOVE_SPI1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x14600)
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							|  |  |  | /* North-South Bridge */ | 
					
						
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										 |  |  | #define BRIDGE_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x20000)
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							|  |  |  | #define BRIDGE_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x20000)
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										 |  |  | #define  BRIDGE_WINS_BASE       (BRIDGE_PHYS_BASE)
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							|  |  |  | #define  BRIDGE_WINS_SZ         (0x80)
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							|  |  |  | /* Cryptographic Engine */ | 
					
						
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										 |  |  | #define DOVE_CRYPT_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x30000)
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							|  |  |  | /* PCIe 0 */ | 
					
						
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										 |  |  | #define DOVE_PCIE0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x40000)
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							|  |  |  | /* USB */ | 
					
						
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										 |  |  | #define DOVE_USB0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x50000)
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							|  |  |  | #define DOVE_USB1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x51000)
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							|  |  |  | /* XOR 0 Engine */ | 
					
						
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										 |  |  | #define DOVE_XOR0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60800)
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							|  |  |  | #define DOVE_XOR0_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60800)
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							|  |  |  | #define DOVE_XOR0_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60A00)
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							|  |  |  | #define DOVE_XOR0_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60A00)
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							|  |  |  | /* XOR 1 Engine */ | 
					
						
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										 |  |  | #define DOVE_XOR1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60900)
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							|  |  |  | #define DOVE_XOR1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60900)
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							|  |  |  | #define DOVE_XOR1_HIGH_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x60B00)
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							|  |  |  | #define DOVE_XOR1_HIGH_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x60B00)
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							|  |  |  | /* Gigabit Ethernet */ | 
					
						
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										 |  |  | #define DOVE_GE00_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x70000)
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							|  |  |  | /* PCIe 1 */ | 
					
						
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										 |  |  | #define DOVE_PCIE1_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0x80000)
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							|  |  |  | /* CAFE */ | 
					
						
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										 |  |  | #define DOVE_SDIO0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x92000)
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							|  |  |  | #define DOVE_SDIO1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x90000)
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							|  |  |  | #define DOVE_CAM_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x94000)
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							|  |  |  | #define DOVE_CAFE_WIN_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0x98000)
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							|  |  |  | /* SATA */ | 
					
						
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										 |  |  | #define DOVE_SATA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xa0000)
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							|  |  |  | /* I2S/SPDIF */ | 
					
						
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										 |  |  | #define DOVE_AUD0_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb0000)
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							|  |  |  | #define DOVE_AUD1_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xb4000)
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							|  |  |  | /* NAND Flash Controller */ | 
					
						
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										 |  |  | #define DOVE_NFC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xc0000)
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							|  |  |  | /* MPP, GPIO, Reset Sampling */ | 
					
						
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										 |  |  | #define DOVE_MPP_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0200)
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										 |  |  | #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
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										 |  |  | #define DOVE_RESET_SAMPLE_LO	(DOVE_MPP_VIRT_BASE + 0x014)
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							|  |  |  | #define DOVE_RESET_SAMPLE_HI	(DOVE_MPP_VIRT_BASE + 0x018)
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							|  |  |  | #define DOVE_GPIO_LO_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0400)
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							|  |  |  | #define DOVE_GPIO_HI_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0420)
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							|  |  |  | #define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
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							|  |  |  | #define DOVE_MPP_GENERAL_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe803c)
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										 |  |  | #define  DOVE_AU1_SPDIFO_GPIO_EN	(1 << 1)
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							|  |  |  | #define  DOVE_NAND_GPIO_EN		(1 << 0)
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										 |  |  | #define DOVE_MPP_CTRL4_VIRT_BASE	(DOVE_GPIO_LO_VIRT_BASE + 0x40)
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										 |  |  | #define  DOVE_SPI_GPIO_SEL		(1 << 5)
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							|  |  |  | #define  DOVE_UART1_GPIO_SEL		(1 << 4)
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							|  |  |  | #define  DOVE_AU1_GPIO_SEL		(1 << 3)
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							|  |  |  | #define  DOVE_CAM_GPIO_SEL		(1 << 2)
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							|  |  |  | #define  DOVE_SD1_GPIO_SEL		(1 << 1)
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							|  |  |  | #define  DOVE_SD0_GPIO_SEL		(1 << 0)
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							|  |  |  | /* Power Management */ | 
					
						
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										 |  |  | #define DOVE_PMU_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xd0000)
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										 |  |  | #define DOVE_PMU_SIG_CTRL	(DOVE_PMU_VIRT_BASE + 0x802c)
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							|  |  |  | /* Real Time Clock */ | 
					
						
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										 |  |  | #define DOVE_RTC_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xd8500)
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							|  |  |  | /* AC97 */ | 
					
						
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										 |  |  | #define DOVE_AC97_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe0000)
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							|  |  |  | #define DOVE_AC97_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe0000)
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							|  |  |  | /* Peripheral DMA */ | 
					
						
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										 |  |  | #define DOVE_PDMA_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xe4000)
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							|  |  |  | #define DOVE_PDMA_VIRT_BASE	(DOVE_SB_REGS_VIRT_BASE + 0xe4000)
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										 |  |  | #define DOVE_GLOBAL_CONFIG_1	(DOVE_SB_REGS_VIRT_BASE + 0xe802C)
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										 |  |  | #define  DOVE_TWSI_ENABLE_OPTION1	(1 << 7)
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										 |  |  | #define DOVE_GLOBAL_CONFIG_2	(DOVE_SB_REGS_VIRT_BASE + 0xe8030)
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										 |  |  | #define  DOVE_TWSI_ENABLE_OPTION2	(1 << 20)
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							|  |  |  | #define  DOVE_TWSI_ENABLE_OPTION3	(1 << 21)
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							|  |  |  | #define  DOVE_TWSI_OPTION3_GPIO		(1 << 22)
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										 |  |  | #define DOVE_SSP_PHYS_BASE	(DOVE_SB_REGS_PHYS_BASE + 0xec000)
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							|  |  |  | #define DOVE_SSP_CTRL_STATUS_1	(DOVE_SB_REGS_VIRT_BASE + 0xe8034)
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										 |  |  | #define  DOVE_SSP_ON_AU1		(1 << 0)
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							|  |  |  | #define  DOVE_SSP_CLOCK_ENABLE		(1 << 1)
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							|  |  |  | #define  DOVE_SSP_BPB_CLOCK_SRC_SSP	(1 << 11)
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							|  |  |  | /* Memory Controller */ | 
					
						
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										 |  |  | #define DOVE_MC_PHYS_BASE       (DOVE_NB_REGS_PHYS_BASE + 0x00000)
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							|  |  |  | #define  DOVE_MC_WINS_BASE      (DOVE_MC_PHYS_BASE + 0x100)
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							|  |  |  | #define  DOVE_MC_WINS_SZ        (0x8)
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										 |  |  | #define DOVE_MC_VIRT_BASE	(DOVE_NB_REGS_VIRT_BASE + 0x00000)
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							|  |  |  | /* LCD Controller */ | 
					
						
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										 |  |  | #define DOVE_LCD_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)
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							|  |  |  | #define DOVE_LCD1_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x20000)
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							|  |  |  | #define DOVE_LCD2_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x10000)
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							|  |  |  | #define DOVE_LCD_DCON_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x30000)
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							|  |  |  | /* Graphic Engine */ | 
					
						
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										 |  |  | #define DOVE_GPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x40000)
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							|  |  |  | /* Video Engine */ | 
					
						
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										 |  |  | #define DOVE_VPU_PHYS_BASE	(DOVE_NB_REGS_PHYS_BASE + 0x400000)
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							|  |  |  | #endif
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