2009-05-28 14:03:59 -07:00
										 
									 
								 
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								/*
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								 * SDRC register values for the Micron MT46H32M32LF-6
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								 *
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								 * Copyright (C) 2008 Texas Instruments, Inc.
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								 * Copyright (C) 2008-2009 Nokia Corporation
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								 *
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								 * Paul Walmsley
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								 *
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								 * This program is free software; you can redistribute it and/or modify
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								 * it under the terms of the GNU General Public License version 2 as
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								 * published by the Free Software Foundation.
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								 */
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								#ifndef ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
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								#define ARCH_ARM_MACH_OMAP2_SDRAM_MICRON_MT46H32M32LF
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											2012-10-17 00:46:45 +00:00
										 
									 
								 
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								#include "sdrc.h"
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								/* Micron MT46H32M32LF-6 */
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								/* XXX Using ARE = 0x1 (no autorefresh burst) -- can this be changed? */
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								static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
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									[0] = {
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										.rate	     = 166000000,
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										.actim_ctrla = 0x9a9db4c6,
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										.actim_ctrlb = 0x00011217,
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										.rfr_ctrl    = 0x0004dc01,
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										.mr	     = 0x00000032,
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									},
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									[1] = {
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										.rate	     = 165941176,
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										.actim_ctrla = 0x9a9db4c6,
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										.actim_ctrlb = 0x00011217,
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										.rfr_ctrl    = 0x0004dc01,
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										.mr	     = 0x00000032,
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									},
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									[2] = {
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										.rate	     = 83000000,
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										.actim_ctrla = 0x51512283,
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										.actim_ctrlb = 0x0001120c,
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										.rfr_ctrl    = 0x00025501,
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										.mr	     = 0x00000032,
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									},
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									[3] = {
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										.rate	     = 82970588,
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										.actim_ctrla = 0x51512283,
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										.actim_ctrlb = 0x0001120c,
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										.rfr_ctrl    = 0x00025501,
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										.mr	     = 0x00000032,
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									},
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									[4] = {
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										.rate	     = 0
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									},
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								};
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								#endif
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