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								/******************************************************************************
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								 *
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								 * Copyright(c) 2009-2012  Realtek Corporation.
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								 *
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								 * This program is free software; you can redistribute it and/or modify it
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								 * under the terms of version 2 of the GNU General Public License as
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								 * published by the Free Software Foundation.
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								 *
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								 * This program is distributed in the hope that it will be useful, but WITHOUT
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								 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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								 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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								 * more details.
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								 *
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								 * You should have received a copy of the GNU General Public License along with
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								 * this program; if not, write to the Free Software Foundation, Inc.,
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								 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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								 *
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								 * The full GNU General Public License is included in this distribution in the
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								 * file called LICENSE.
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								 *
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								 * Contact Information:
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								 * wlanfae <wlanfae@realtek.com>
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								 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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								 * Hsinchu 300, Taiwan.
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								 *
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								 * Larry Finger <Larry.Finger@lwfinger.net>
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								 *
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								 *****************************************************************************/
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								#ifndef	__RTL8723E_DM_H__
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								#define __RTL8723E_DM_H__
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								#define HAL_DM_DIG_DISABLE			BIT(0)
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								#define HAL_DM_HIPWR_DISABLE			BIT(1)
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								#define OFDM_TABLE_LENGTH			37
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								#define CCK_TABLE_LENGTH			33
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								#define OFDM_TABLE_SIZE				37
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								#define CCK_TABLE_SIZE				33
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								#define BW_AUTO_SWITCH_HIGH_LOW			25
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								#define BW_AUTO_SWITCH_LOW_HIGH			30
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								#define DM_DIG_THRESH_HIGH			40
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								#define DM_DIG_THRESH_LOW			35
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								#define DM_FALSEALARM_THRESH_LOW		400
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								#define DM_FALSEALARM_THRESH_HIGH		1000
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								#define DM_DIG_MAX				0x3e
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								#define DM_DIG_MIN				0x1e
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								#define DM_DIG_FA_UPPER				0x32
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								#define DM_DIG_FA_LOWER				0x20
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								#define DM_DIG_FA_TH0				0x20
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								#define DM_DIG_FA_TH1				0x100
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								#define DM_DIG_FA_TH2				0x200
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								#define DM_DIG_BACKOFF_MAX			12
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								#define DM_DIG_BACKOFF_MIN			-4
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								#define DM_DIG_BACKOFF_DEFAULT			10
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								#define RXPATHSELECTION_SS_TH_LOW		30
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								#define RXPATHSELECTION_DIFF_TH			18
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								#define DM_RATR_STA_INIT			0
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								#define DM_RATR_STA_HIGH			1
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								#define DM_RATR_STA_MIDDLE			2
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								#define DM_RATR_STA_LOW				3
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								#define CTS2SELF_THVAL				30
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								#define REGC38_TH				20
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								#define WAIOTTHVAL				25
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								#define TXHIGHPWRLEVEL_NORMAL			0
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								#define TXHIGHPWRLEVEL_LEVEL1			1
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								#define TXHIGHPWRLEVEL_LEVEL2			2
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								#define TXHIGHPWRLEVEL_BT1			3
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								#define TXHIGHPWRLEVEL_BT2			4
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								#define DM_TYPE_BYFW				0
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								#define DM_TYPE_BYDRIVER			1
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								#define TX_POWER_NEAR_FIELD_THRESH_LVL2		74
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								#define TX_POWER_NEAR_FIELD_THRESH_LVL1		67
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								struct swat_t {
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									u8 failure_cnt;
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									u8 try_flag;
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									u8 stop_trying;
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									long pre_rssi;
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									long trying_threshold;
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									u8 cur_antenna;
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									u8 pre_antenna;
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								};
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								enum tag_dynamic_init_gain_operation_type_definition {
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									DIG_TYPE_THRESH_HIGH = 0,
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									DIG_TYPE_THRESH_LOW = 1,
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									DIG_TYPE_BACKOFF = 2,
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									DIG_TYPE_RX_GAIN_MIN = 3,
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									DIG_TYPE_RX_GAIN_MAX = 4,
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									DIG_TYPE_ENABLE = 5,
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									DIG_TYPE_DISABLE = 6,
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									DIG_OP_TYPE_MAX
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								};
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								enum tag_cck_packet_detection_threshold_type_definition {
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									CCK_PD_STAGE_LowRssi = 0,
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									CCK_PD_STAGE_HighRssi = 1,
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									CCK_FA_STAGE_LOW = 2,
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									CCK_FA_STAGE_High = 3,
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									CCK_PD_STAGE_MAX = 4,
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								};
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								enum dm_1r_cca_e {
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									CCA_1R = 0,
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									CCA_2R = 1,
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									CCA_MAX = 2,
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								};
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								enum dm_rf_e {
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									RF_SAVE = 0,
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									RF_NORMAL = 1,
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									RF_MAX = 2,
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								};
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								enum dm_sw_ant_switch_e {
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									ANS_ANTENNA_B = 1,
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									ANS_ANTENNA_A = 2,
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									ANS_ANTENNA_MAX = 3,
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								};
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								enum dm_dig_ext_port_alg_e {
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									DIG_EXT_PORT_STAGE_0 = 0,
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									DIG_EXT_PORT_STAGE_1 = 1,
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									DIG_EXT_PORT_STAGE_2 = 2,
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									DIG_EXT_PORT_STAGE_3 = 3,
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									DIG_EXT_PORT_STAGE_MAX = 4,
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								};
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								enum dm_dig_connect_e {
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									DIG_STA_DISCONNECT = 0,
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									DIG_STA_CONNECT = 1,
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									DIG_STA_BEFORE_CONNECT = 2,
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									DIG_MULTISTA_DISCONNECT = 3,
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									DIG_MULTISTA_CONNECT = 4,
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									DIG_CONNECT_MAX
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								};
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								#define BT_RSSI_STATE_NORMAL_POWER      BIT_OFFSET_LEN_MASK_32(0, 1)
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								#define BT_RSSI_STATE_AMDPU_OFF         BIT_OFFSET_LEN_MASK_32(1, 1)
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								#define BT_RSSI_STATE_SPECIAL_LOW       BIT_OFFSET_LEN_MASK_32(2, 1)
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								#define BT_RSSI_STATE_BG_EDCA_LOW       BIT_OFFSET_LEN_MASK_32(3, 1)
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								#define BT_RSSI_STATE_TXPOWER_LOW       BIT_OFFSET_LEN_MASK_32(4, 1)
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								#define GET_UNDECORATED_AVERAGE_RSSI(_priv)     \
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									( \
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									(((struct rtl_priv *)(_priv))->mac80211.opmode ==		\
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											     NL80211_IFTYPE_ADHOC) ?			\
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									(((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) :	\
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									(((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb)		\
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									)
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								void rtl8723e_dm_init(struct ieee80211_hw *hw);
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								void rtl8723e_dm_watchdog(struct ieee80211_hw *hw);
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								void rtl8723e_dm_write_dig(struct ieee80211_hw *hw);
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								void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
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								void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
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								void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
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								void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw);
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								#endif
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