| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  | /*
 | 
					
						
							| 
									
										
										
										
											2008-04-30 23:29:04 +04:00
										 |  |  |  * AMD Alchemy DBAu1200 Reference Board | 
					
						
							|  |  |  |  * Board register defines. | 
					
						
							| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  |  * | 
					
						
							|  |  |  |  * ######################################################################## | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  *  This program is free software; you can distribute it and/or modify it | 
					
						
							|  |  |  |  *  under the terms of the GNU General Public License (Version 2) as | 
					
						
							|  |  |  |  *  published by the Free Software Foundation. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  *  This program is distributed in the hope it will be useful, but WITHOUT | 
					
						
							|  |  |  |  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | 
					
						
							|  |  |  |  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License | 
					
						
							|  |  |  |  *  for more details. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  *  You should have received a copy of the GNU General Public License along | 
					
						
							|  |  |  |  *  with this program; if not, write to the Free Software Foundation, Inc., | 
					
						
							|  |  |  |  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * ######################################################################## | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #ifndef __ASM_DB1200_H
 | 
					
						
							|  |  |  | #define __ASM_DB1200_H
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #include <linux/types.h>
 | 
					
						
							| 
									
										
										
										
											2009-10-04 14:55:26 +02:00
										 |  |  | #include <asm/mach-au1x00/au1000.h>
 | 
					
						
							| 
									
										
										
										
											2008-02-24 20:03:42 +01:00
										 |  |  | #include <asm/mach-au1x00/au1xxx_psc.h>
 | 
					
						
							| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  | 
 | 
					
						
							|  |  |  | /* Bit positions for the different interrupt sources */ | 
					
						
							|  |  |  | #define BCSR_INT_IDE		0x0001
 | 
					
						
							|  |  |  | #define BCSR_INT_ETH		0x0002
 | 
					
						
							|  |  |  | #define BCSR_INT_PC0		0x0004
 | 
					
						
							|  |  |  | #define BCSR_INT_PC0STSCHG	0x0008
 | 
					
						
							|  |  |  | #define BCSR_INT_PC1		0x0010
 | 
					
						
							|  |  |  | #define BCSR_INT_PC1STSCHG	0x0020
 | 
					
						
							| 
									
										
										
										
											2008-04-30 23:29:04 +04:00
										 |  |  | #define BCSR_INT_DC		0x0040
 | 
					
						
							| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  | #define BCSR_INT_FLASHBUSY	0x0080
 | 
					
						
							|  |  |  | #define BCSR_INT_PC0INSERT	0x0100
 | 
					
						
							|  |  |  | #define BCSR_INT_PC0EJECT	0x0200
 | 
					
						
							|  |  |  | #define BCSR_INT_PC1INSERT	0x0400
 | 
					
						
							|  |  |  | #define BCSR_INT_PC1EJECT	0x0800
 | 
					
						
							|  |  |  | #define BCSR_INT_SD0INSERT	0x1000
 | 
					
						
							|  |  |  | #define BCSR_INT_SD0EJECT	0x2000
 | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2008-04-28 19:54:38 +04:00
										 |  |  | #define IDE_PHYS_ADDR		0x18800000
 | 
					
						
							|  |  |  | #define IDE_REG_SHIFT		5
 | 
					
						
							|  |  |  | #define IDE_DDMA_REQ		DSCR_CMD0_DMA_REQ1
 | 
					
						
							|  |  |  | #define IDE_RQSIZE		128
 | 
					
						
							| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2009-11-02 21:21:43 +01:00
										 |  |  | #define DB1200_IDE_PHYS_ADDR	IDE_PHYS_ADDR
 | 
					
						
							|  |  |  | #define DB1200_IDE_PHYS_LEN	(16 << IDE_REG_SHIFT)
 | 
					
						
							|  |  |  | #define DB1200_ETH_PHYS_ADDR	0x19000300
 | 
					
						
							|  |  |  | #define DB1200_NAND_PHYS_ADDR	0x20000000
 | 
					
						
							| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							| 
									
										
										
										
											2008-04-30 23:29:04 +04:00
										 |  |  |  * External Interrupts for DBAu1200 as of 8/6/2004. | 
					
						
							| 
									
										
										
										
											2007-10-17 15:38:30 +01:00
										 |  |  |  * Bit positions in the CPLD registers can be calculated by taking | 
					
						
							|  |  |  |  * the interrupt define and subtracting the DB1200_INT_BEGIN value. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  *   Example: IDE bis pos is  = 64 - 64 | 
					
						
							|  |  |  |  *            ETH bit pos is  = 65 - 64 | 
					
						
							| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  |  */ | 
					
						
							| 
									
										
										
										
											2009-11-02 21:21:43 +01:00
										 |  |  | enum external_db1200_ints { | 
					
						
							| 
									
										
										
										
											2007-10-17 15:38:30 +01:00
										 |  |  | 	DB1200_INT_BEGIN	= AU1000_MAX_INTR + 1, | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	DB1200_IDE_INT		= DB1200_INT_BEGIN, | 
					
						
							|  |  |  | 	DB1200_ETH_INT, | 
					
						
							|  |  |  | 	DB1200_PC0_INT, | 
					
						
							|  |  |  | 	DB1200_PC0_STSCHG_INT, | 
					
						
							|  |  |  | 	DB1200_PC1_INT, | 
					
						
							|  |  |  | 	DB1200_PC1_STSCHG_INT, | 
					
						
							|  |  |  | 	DB1200_DC_INT, | 
					
						
							|  |  |  | 	DB1200_FLASHBUSY_INT, | 
					
						
							|  |  |  | 	DB1200_PC0_INSERT_INT, | 
					
						
							|  |  |  | 	DB1200_PC0_EJECT_INT, | 
					
						
							|  |  |  | 	DB1200_PC1_INSERT_INT, | 
					
						
							|  |  |  | 	DB1200_PC1_EJECT_INT, | 
					
						
							|  |  |  | 	DB1200_SD0_INSERT_INT, | 
					
						
							|  |  |  | 	DB1200_SD0_EJECT_INT, | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | 	DB1200_INT_END		= DB1200_INT_BEGIN + 15, | 
					
						
							|  |  |  | }; | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2005-03-01 06:33:16 +00:00
										 |  |  | #endif /* __ASM_DB1200_H */
 |