2007-02-10 01:43:40 -08:00
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#ifndef _M32700UT_M32700UT_LAN_H
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#define _M32700UT_M32700UT_LAN_H
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2005-04-16 15:20:36 -07:00
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/*
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2006-10-03 23:01:26 +02:00
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* include/asm-m32r/m32700ut/m32700ut_lan.h
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2005-04-16 15:20:36 -07:00
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*
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* M32700UT-LAN board
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*
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* Copyright (c) 2002 Takeo Takahashi
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*/
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#ifndef __ASSEMBLY__
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/*
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* C functions use non-cache address.
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*/
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#define M32700UT_LAN_BASE (0x10000000 /* + NONCACHE_OFFSET */)
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#else
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#define M32700UT_LAN_BASE (0x10000000 + NONCACHE_OFFSET)
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2007-02-10 01:43:40 -08:00
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#endif /* __ASSEMBLY__ */
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2005-04-16 15:20:36 -07:00
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/* ICU
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* ICUISTS: status register
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* ICUIREQ0: request register
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* ICUIREQ1: request register
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* ICUCR3: control register for CFIREQ# interrupt
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* ICUCR4: control register for CFC Card insert interrupt
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* ICUCR5: control register for CFC Card eject interrupt
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* ICUCR6: control register for external interrupt
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* ICUCR11: control register for MMC Card insert/eject interrupt
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* ICUCR13: control register for SC error interrupt
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* ICUCR14: control register for SC receive interrupt
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* ICUCR15: control register for SC send interrupt
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* ICUCR16: control register for SIO0 receive interrupt
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* ICUCR17: control register for SIO0 send interrupt
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*/
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#define M32700UT_LAN_IRQ_LAN (M32700UT_LAN_PLD_IRQ_BASE + 1) /* LAN */
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#define M32700UT_LAN_IRQ_I2C (M32700UT_LAN_PLD_IRQ_BASE + 3) /* I2C */
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#define M32700UT_LAN_ICUISTS __reg16(M32700UT_LAN_BASE + 0xc0002)
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#define M32700UT_LAN_ICUISTS_VECB_MASK (0xf000)
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#define M32700UT_LAN_VECB(x) ((x) & M32700UT_LAN_ICUISTS_VECB_MASK)
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#define M32700UT_LAN_ICUISTS_ISN_MASK (0x07c0)
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#define M32700UT_LAN_ICUISTS_ISN(x) ((x) & M32700UT_LAN_ICUISTS_ISN_MASK)
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#define M32700UT_LAN_ICUIREQ0 __reg16(M32700UT_LAN_BASE + 0xc0004)
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#define M32700UT_LAN_ICUCR1 __reg16(M32700UT_LAN_BASE + 0xc0010)
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#define M32700UT_LAN_ICUCR3 __reg16(M32700UT_LAN_BASE + 0xc0014)
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/*
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* AR register on PLD
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*/
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#define ARVCR0 __reg32(M32700UT_LAN_BASE + 0x40000)
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#define ARVCR0_VDS 0x00080000
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#define ARVCR0_RST 0x00010000
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#define ARVCR1 __reg32(M32700UT_LAN_BASE + 0x40004)
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#define ARVCR1_QVGA 0x02000000
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#define ARVCR1_NORMAL 0x01000000
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#define ARVCR1_HIEN 0x00010000
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#define ARVHCOUNT __reg32(M32700UT_LAN_BASE + 0x40008)
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#define ARDATA __reg32(M32700UT_LAN_BASE + 0x40010)
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#define ARINTSEL __reg32(M32700UT_LAN_BASE + 0x40014)
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#define ARINTSEL_INT3 0x10000000 /* CPU INT3 */
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#define ARDATA32 __reg32(M32700UT_LAN_BASE + 0x04040010) // Block 5
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/*
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#define ARINTSEL_SEL2 0x00002000
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#define ARINTSEL_SEL3 0x00001000
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#define ARINTSEL_SEL6 0x00000200
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#define ARINTSEL_SEL7 0x00000100
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#define ARINTSEL_SEL9 0x00000040
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#define ARINTSEL_SEL10 0x00000020
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#define ARINTSEL_SEL11 0x00000010
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#define ARINTSEL_SEL12 0x00000008
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*/
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/*
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* I2C register on PLD
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*/
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#define PLDI2CCR __reg32(M32700UT_LAN_BASE + 0x40040)
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#define PLDI2CCR_ES0 0x00000001 /* enable I2C interface */
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#define PLDI2CMOD __reg32(M32700UT_LAN_BASE + 0x40044)
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#define PLDI2CMOD_ACKCLK 0x00000200
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#define PLDI2CMOD_DTWD 0x00000100
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#define PLDI2CMOD_10BT 0x00000004
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#define PLDI2CMOD_ATM_NORMAL 0x00000000
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#define PLDI2CMOD_ATM_AUTO 0x00000003
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#define PLDI2CACK __reg32(M32700UT_LAN_BASE + 0x40048)
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#define PLDI2CACK_ACK 0x00000001
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#define PLDI2CFREQ __reg32(M32700UT_LAN_BASE + 0x4004c)
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#define PLDI2CCND __reg32(M32700UT_LAN_BASE + 0x40050)
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#define PLDI2CCND_START 0x00000001
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#define PLDI2CCND_STOP 0x00000002
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#define PLDI2CSTEN __reg32(M32700UT_LAN_BASE + 0x40054)
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#define PLDI2CSTEN_STEN 0x00000001
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#define PLDI2CDATA __reg32(M32700UT_LAN_BASE + 0x40060)
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#define PLDI2CSTS __reg32(M32700UT_LAN_BASE + 0x40064)
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#define PLDI2CSTS_TRX 0x00000020
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#define PLDI2CSTS_BB 0x00000010
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#define PLDI2CSTS_NOACK 0x00000001 /* 0:ack, 1:noack */
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2007-02-10 01:43:40 -08:00
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#endif /* _M32700UT_M32700UT_LAN_H */
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