linux-pinenote/arch/mips/include/asm/mach-loongson1/regs-clk.h

/*
 * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
 *
 * Loongson 1 Clock Register Definitions.
 *
 * This program is free software; you can redistribute	it and/or modify it
 * under  the terms of	the GNU General	 Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H
#define __ASM_MACH_LOONGSON1_REGS_CLK_H

#define LS1X_CLK_REG(x) \
		((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))

#define LS1X_CLK_PLL_FREQ		LS1X_CLK_REG(0x0)
#define LS1X_CLK_PLL_DIV		LS1X_CLK_REG(0x4)

/* Clock PLL Divisor Register Bits */
#define DIV_DC_EN			(0x1 << 31)
#define DIV_CPU_EN			(0x1 << 25)
#define DIV_DDR_EN			(0x1 << 19)

#define DIV_DC_SHIFT			26
#define DIV_CPU_SHIFT			20
#define DIV_DDR_SHIFT			14

#define DIV_DC_WIDTH			5
#define DIV_CPU_WIDTH			5
#define DIV_DDR_WIDTH			5

#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */
MIPS: Loongson 1B: Add board support Adds basic platform devices for Loongson 1B, including serial port, ethernet, USB, RTC and interrupt handler. The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is built around a Synopsys IP Core. Use normal instead of enhanced descriptors. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4133/ Patchwork: https://patchwork.linux-mips.org/patch/4134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2012-07-25 16:17:24 +02:00			`/*`
			`* Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>`
			`*`
			`* Loongson 1 Clock Register Definitions.`
			`*`
MIPS: Whitespace cleanup. Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2013-01-22 12:59:30 +01:00			`* This program is free software; you can redistribute it and/or modify it`
			`* under the terms of the GNU General Public License as published by the`
MIPS: Loongson 1B: Add board support Adds basic platform devices for Loongson 1B, including serial port, ethernet, USB, RTC and interrupt handler. The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is built around a Synopsys IP Core. Use normal instead of enhanced descriptors. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4133/ Patchwork: https://patchwork.linux-mips.org/patch/4134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2012-07-25 16:17:24 +02:00			`* Free Software Foundation; either version 2 of the License, or (at your`
			`* option) any later version.`
			`*/`

			`#ifndef __ASM_MACH_LOONGSON1_REGS_CLK_H`
			`#define __ASM_MACH_LOONGSON1_REGS_CLK_H`

			`#define LS1X_CLK_REG(x) \`
			`((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x)))`

			`#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)`
			`#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)`

			`/* Clock PLL Divisor Register Bits */`
			`#define DIV_DC_EN (0x1 << 31)`
			`#define DIV_CPU_EN (0x1 << 25)`
			`#define DIV_DDR_EN (0x1 << 19)`

			`#define DIV_DC_SHIFT 26`
			`#define DIV_CPU_SHIFT 20`
			`#define DIV_DDR_SHIFT 14`

MIPS: Loongson1B: use common clock infrastructure instead of private APIs Use common clock infrastructure instead of private APIs. 1. Enable COMMON_CLK in the Kconfig. 2. Remove private clock APIs, which are replaced by the code in drivers/clk/clk-ls1x.c. 3. Modify header file for drivers/clk/clk-ls1x.c. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4431 Signed-off-by: John Crispin <blogic@openwrt.org> 2012-10-23 05:17:00 +00:00			`#define DIV_DC_WIDTH 5`
			`#define DIV_CPU_WIDTH 5`
			`#define DIV_DDR_WIDTH 5`

MIPS: Loongson 1B: Add board support Adds basic platform devices for Loongson 1B, including serial port, ethernet, USB, RTC and interrupt handler. The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is built around a Synopsys IP Core. Use normal instead of enhanced descriptors. Thanks to Giuseppe for updating the normal descriptor in stmmac driver. Thanks to Zhao Zhang for implementing the RTC driver. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/4133/ Patchwork: https://patchwork.linux-mips.org/patch/4134/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2012-07-25 16:17:24 +02:00			`#endif /* __ASM_MACH_LOONGSON1_REGS_CLK_H */`