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											2007-10-11 11:17:24 +02:00
										 |  |  | /*
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											2007-10-12 21:10:53 -04:00
										 |  |  |  * check TSC synchronization. | 
					
						
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											2007-10-11 11:17:24 +02:00
										 |  |  |  * | 
					
						
							|  |  |  |  * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * We check whether all boot CPUs have their TSC's synchronized, | 
					
						
							|  |  |  |  * print a warning if not and turn off the TSC clock-source. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * The warp-check is point-to-point between two CPUs, the CPU | 
					
						
							|  |  |  |  * initiating the bootup is the 'source CPU', the freshly booting | 
					
						
							|  |  |  |  * CPU is the 'target CPU'. | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Only two CPUs may participate - they can enter in any order. | 
					
						
							|  |  |  |  * ( The serial nature of the boot logic and the CPU hotplug lock | 
					
						
							|  |  |  |  *   protects against more than 2 CPUs entering this code. ) | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #include <linux/spinlock.h>
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							|  |  |  | #include <linux/kernel.h>
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							|  |  |  | #include <linux/init.h>
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							|  |  |  | #include <linux/smp.h>
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							|  |  |  | #include <linux/nmi.h>
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							|  |  |  | #include <asm/tsc.h>
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							|  |  |  | 
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							|  |  |  | /*
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							|  |  |  |  * Entry/exit counters that make sure that both CPUs | 
					
						
							|  |  |  |  * run the measurement code at once: | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | static __cpuinitdata atomic_t start_count; | 
					
						
							|  |  |  | static __cpuinitdata atomic_t stop_count; | 
					
						
							|  |  |  | 
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							|  |  |  | /*
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							|  |  |  |  * We use a raw spinlock in this exceptional case, because | 
					
						
							|  |  |  |  * we want to have the fastest, inlined, non-debug version | 
					
						
							|  |  |  |  * of a critical section, to be able to prove TSC time-warps: | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | static __cpuinitdata raw_spinlock_t sync_lock = __RAW_SPIN_LOCK_UNLOCKED; | 
					
						
							|  |  |  | static __cpuinitdata cycles_t last_tsc; | 
					
						
							|  |  |  | static __cpuinitdata cycles_t max_warp; | 
					
						
							|  |  |  | static __cpuinitdata int nr_warps; | 
					
						
							|  |  |  | 
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							|  |  |  | /*
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							|  |  |  |  * TSC-warp measurement loop running on both CPUs: | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | static __cpuinit void check_tsc_warp(void) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	cycles_t start, now, prev, end; | 
					
						
							|  |  |  | 	int i; | 
					
						
							|  |  |  | 
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										 |  |  | 	start = get_cycles(); | 
					
						
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										 |  |  | 	/*
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							|  |  |  | 	 * The measurement runs for 20 msecs: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	end = start + tsc_khz * 20ULL; | 
					
						
							|  |  |  | 	now = start; | 
					
						
							|  |  |  | 
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							|  |  |  | 	for (i = 0; ; i++) { | 
					
						
							|  |  |  | 		/*
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							|  |  |  | 		 * We take the global lock, measure TSC, save the | 
					
						
							|  |  |  | 		 * previous TSC that was measured (possibly on | 
					
						
							|  |  |  | 		 * another CPU) and update the previous TSC timestamp. | 
					
						
							|  |  |  | 		 */ | 
					
						
							|  |  |  | 		__raw_spin_lock(&sync_lock); | 
					
						
							|  |  |  | 		prev = last_tsc; | 
					
						
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										 |  |  | 		now = get_cycles(); | 
					
						
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										 |  |  | 		last_tsc = now; | 
					
						
							|  |  |  | 		__raw_spin_unlock(&sync_lock); | 
					
						
							|  |  |  | 
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							|  |  |  | 		/*
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							|  |  |  | 		 * Be nice every now and then (and also check whether | 
					
						
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										 |  |  | 		 * measurement is done [we also insert a 10 million | 
					
						
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										 |  |  | 		 * loops safety exit, so we dont lock up in case the | 
					
						
							|  |  |  | 		 * TSC readout is totally broken]): | 
					
						
							|  |  |  | 		 */ | 
					
						
							|  |  |  | 		if (unlikely(!(i & 7))) { | 
					
						
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										 |  |  | 			if (now > end || i > 10000000) | 
					
						
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										 |  |  | 				break; | 
					
						
							|  |  |  | 			cpu_relax(); | 
					
						
							|  |  |  | 			touch_nmi_watchdog(); | 
					
						
							|  |  |  | 		} | 
					
						
							|  |  |  | 		/*
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							|  |  |  | 		 * Outside the critical section we can now see whether | 
					
						
							|  |  |  | 		 * we saw a time-warp of the TSC going backwards: | 
					
						
							|  |  |  | 		 */ | 
					
						
							|  |  |  | 		if (unlikely(prev > now)) { | 
					
						
							|  |  |  | 			__raw_spin_lock(&sync_lock); | 
					
						
							|  |  |  | 			max_warp = max(max_warp, prev - now); | 
					
						
							|  |  |  | 			nr_warps++; | 
					
						
							|  |  |  | 			__raw_spin_unlock(&sync_lock); | 
					
						
							|  |  |  | 		} | 
					
						
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										 |  |  | 	} | 
					
						
							|  |  |  | 	if (!(now-start)) { | 
					
						
							|  |  |  | 		printk("Warning: zero tsc calibration delta: %Ld [max: %Ld]\n", | 
					
						
							|  |  |  | 			now-start, end-start); | 
					
						
							|  |  |  | 		WARN_ON(1); | 
					
						
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										 |  |  | 	} | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | 
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							|  |  |  | /*
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							|  |  |  |  * Source CPU calls into this - it waits for the freshly booted | 
					
						
							|  |  |  |  * target CPU to arrive and then starts the measurement: | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | void __cpuinit check_tsc_sync_source(int cpu) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	int cpus = 2; | 
					
						
							|  |  |  | 
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							|  |  |  | 	/*
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							|  |  |  | 	 * No need to check if we already know that the TSC is not | 
					
						
							|  |  |  | 	 * synchronized: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	if (unsynchronized_tsc()) | 
					
						
							|  |  |  | 		return; | 
					
						
							|  |  |  | 
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							|  |  |  | 	printk(KERN_INFO "checking TSC synchronization [CPU#%d -> CPU#%d]:", | 
					
						
							|  |  |  | 			  smp_processor_id(), cpu); | 
					
						
							|  |  |  | 
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							|  |  |  | 	/*
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							|  |  |  | 	 * Reset it - in case this is a second bootup: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	atomic_set(&stop_count, 0); | 
					
						
							|  |  |  | 
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							|  |  |  | 	/*
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							|  |  |  | 	 * Wait for the target to arrive: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	while (atomic_read(&start_count) != cpus-1) | 
					
						
							|  |  |  | 		cpu_relax(); | 
					
						
							|  |  |  | 	/*
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							|  |  |  | 	 * Trigger the target to continue into the measurement too: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	atomic_inc(&start_count); | 
					
						
							|  |  |  | 
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							|  |  |  | 	check_tsc_warp(); | 
					
						
							|  |  |  | 
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							|  |  |  | 	while (atomic_read(&stop_count) != cpus-1) | 
					
						
							|  |  |  | 		cpu_relax(); | 
					
						
							|  |  |  | 
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							|  |  |  | 	if (nr_warps) { | 
					
						
							|  |  |  | 		printk("\n"); | 
					
						
							|  |  |  | 		printk(KERN_WARNING "Measured %Ld cycles TSC warp between CPUs," | 
					
						
							|  |  |  | 				    " turning off TSC clock.\n", max_warp); | 
					
						
							|  |  |  | 		mark_tsc_unstable("check_tsc_sync_source failed"); | 
					
						
							|  |  |  | 	} else { | 
					
						
							|  |  |  | 		printk(" passed.\n"); | 
					
						
							|  |  |  | 	} | 
					
						
							|  |  |  | 
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												x86: fix: s2ram + P4 + tsc = annoyance
s2ram recently became useful here, except for the kernel's annoying
habit of disabling my P4's perfectly good TSC.
[  107.894470] CPU 1 is now offline
[  107.894474] SMP alternatives: switching to UP code
[  107.895832] CPU0 attaching sched-domain:
[  107.895836]  domain 0: span 1
[  107.895838]   groups: 1
[  107.896097] CPU1 is down
[    3.726156] Intel machine check architecture supported.
[    3.726165] Intel machine check reporting enabled on CPU#0.
[    3.726167] CPU0: Intel P4/Xeon Extended MCE MSRs (12) available
[    3.726170] CPU0: Thermal monitoring enabled
[    3.726175] Back to C!
[    3.726708] Force enabled HPET at resume
[    3.726775] Enabling non-boot CPUs ...
[    3.727049] CPU0 attaching NULL sched-domain.
[    3.727165] SMP alternatives: switching to SMP code
[    3.727858] Booting processor 1/1 eip 3000
[    3.727862] CPU 1 irqstacks, hard=b042f000 soft=b042d000
[    3.738173] Initializing CPU#1
[    3.798912] Calibrating delay using timer specific routine.. 5986.12 BogoMIPS (lpj=2993061)
[    3.798920] CPU: After generic identify, caps: bfebfbff 00000000 00000000 00000000 00004400 00000000 00000000 00000000
[    3.798931] CPU: Trace cache: 12K uops, L1 D cache: 8K
[    3.798934] CPU: L2 cache: 512K
[    3.798936] CPU: Physical Processor ID: 0
[    3.798938] CPU: After all inits, caps: bfebfbff 00000000 00000000 0000b080 00004400 00000000 00000000 00000000
[    3.798946] Intel machine check architecture supported.
[    3.798952] Intel machine check reporting enabled on CPU#1.
[    3.798955] CPU1: Intel P4/Xeon Extended MCE MSRs (12) available
[    3.798959] CPU1: Thermal monitoring enabled
[    3.799161] CPU1: Intel(R) Pentium(R) 4 CPU 3.00GHz stepping 09
[    3.799187] checking TSC synchronization [CPU#0 -> CPU#1]:
[    3.819181] Measured 63588552840 cycles TSC warp between CPUs, turning off TSC clock.
[    3.819184] Marking TSC unstable due to: check_tsc_sync_source failed.
If check_tsc_warp() is called after initial boot, and the TSC has in the
meantime been set (BIOS, user, silicon, elves) to a value lower than the
last stored/stale value, we blame the TSC.  Reset to pristine condition
after every test.
Signed-off-by: Mike Galbraith <efault@gmx.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
											
										 
											2008-01-30 13:30:04 +01:00
										 |  |  | 	/*
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							|  |  |  | 	 * Reset it - just in case we boot another CPU later: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	atomic_set(&start_count, 0); | 
					
						
							|  |  |  | 	nr_warps = 0; | 
					
						
							|  |  |  | 	max_warp = 0; | 
					
						
							|  |  |  | 	last_tsc = 0; | 
					
						
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										 |  |  | 	/*
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							|  |  |  | 	 * Let the target continue with the bootup: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	atomic_inc(&stop_count); | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | /*
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							|  |  |  |  * Freshly booted CPUs call into this: | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | void __cpuinit check_tsc_sync_target(void) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	int cpus = 2; | 
					
						
							|  |  |  | 
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							|  |  |  | 	if (unsynchronized_tsc()) | 
					
						
							|  |  |  | 		return; | 
					
						
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							|  |  |  | 	/*
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							|  |  |  | 	 * Register this CPU's participation and wait for the | 
					
						
							|  |  |  | 	 * source CPU to start the measurement: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	atomic_inc(&start_count); | 
					
						
							|  |  |  | 	while (atomic_read(&start_count) != cpus) | 
					
						
							|  |  |  | 		cpu_relax(); | 
					
						
							|  |  |  | 
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							|  |  |  | 	check_tsc_warp(); | 
					
						
							|  |  |  | 
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							|  |  |  | 	/*
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							|  |  |  | 	 * Ok, we are done: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	atomic_inc(&stop_count); | 
					
						
							|  |  |  | 
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							|  |  |  | 	/*
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							|  |  |  | 	 * Wait for the source CPU to print stuff: | 
					
						
							|  |  |  | 	 */ | 
					
						
							|  |  |  | 	while (atomic_read(&stop_count) != cpus) | 
					
						
							|  |  |  | 		cpu_relax(); | 
					
						
							|  |  |  | } | 
					
						
							|  |  |  | #undef NR_LOOPS
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							|  |  |  | 
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