2012-07-06 07:36:43 +10:00
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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2015-01-14 15:35:00 +10:00
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#include "priv.h"
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2012-07-06 07:36:43 +10:00
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2012-07-10 10:49:22 +10:00
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#include <subdev/bios.h>
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2012-11-04 01:01:53 +01:00
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#include <subdev/bus.h>
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2012-07-10 12:20:17 +10:00
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#include <subdev/gpio.h>
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2012-07-10 14:36:38 +10:00
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#include <subdev/i2c.h>
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2014-08-26 00:26:38 +02:00
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#include <subdev/fuse.h>
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2015-01-13 23:37:38 +10:00
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#include <subdev/clk.h>
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2012-09-02 02:55:58 +02:00
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#include <subdev/therm.h>
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2012-07-22 16:41:26 +10:00
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#include <subdev/mxm.h>
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2012-07-11 10:44:20 +10:00
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#include <subdev/devinit.h>
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2012-07-11 15:58:56 +10:00
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#include <subdev/mc.h>
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2012-07-11 16:08:25 +10:00
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#include <subdev/timer.h>
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2012-07-11 19:05:01 +10:00
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#include <subdev/fb.h>
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2014-08-10 04:10:28 +10:00
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#include <subdev/ltc.h>
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2012-09-26 13:05:01 +10:00
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#include <subdev/ibus.h>
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2012-07-14 19:09:17 +10:00
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#include <subdev/instmem.h>
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2015-01-14 09:57:36 +10:00
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#include <subdev/mmu.h>
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2012-07-14 19:09:17 +10:00
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#include <subdev/bar.h>
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2015-01-14 00:04:21 +10:00
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#include <subdev/pmu.h>
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2013-02-08 09:34:56 +10:00
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#include <subdev/volt.h>
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2012-07-06 07:36:43 +10:00
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2012-07-20 08:17:34 +10:00
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#include <engine/dmaobj.h>
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#include <engine/fifo.h>
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2015-01-14 12:34:00 +10:00
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#include <engine/sw.h>
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2015-01-14 12:02:28 +10:00
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#include <engine/gr.h>
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2015-01-14 12:50:04 +10:00
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#include <engine/mspdec.h>
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2012-07-20 08:17:34 +10:00
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#include <engine/bsp.h>
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2015-01-14 10:09:24 +10:00
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#include <engine/msvld.h>
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2015-01-14 12:26:28 +10:00
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#include <engine/msppp.h>
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2015-01-14 11:50:20 +10:00
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#include <engine/ce.h>
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2012-07-20 08:17:34 +10:00
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#include <engine/disp.h>
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2015-01-14 12:11:28 +10:00
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#include <engine/pm.h>
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2012-07-20 08:17:34 +10:00
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2012-07-06 07:36:43 +10:00
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int
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2015-01-14 15:35:00 +10:00
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gf100_identify(struct nvkm_device *device)
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2012-07-06 07:36:43 +10:00
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{
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switch (device->chipset) {
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case 0xc0:
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2012-07-27 08:28:20 +10:00
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device->cname = "GF100";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2015-01-14 15:02:59 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 15:04:16 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-26 00:26:38 +02:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 14:47:24 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2015-01-14 15:11:48 +10:00
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 14:48:16 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 15:08:21 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
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2015-01-14 14:40:22 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 14:52:58 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-10 04:10:28 +10:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 15:04:31 +10:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 15:09:19 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 14:35:35 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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2015-01-14 15:10:40 +10:00
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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2013-02-08 09:34:56 +10:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2015-01-14 15:27:54 +10:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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2015-01-14 15:28:47 +10:00
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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2015-01-14 15:32:15 +10:00
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device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
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2015-01-14 15:29:43 +10:00
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device->oclass[NVDEV_ENGINE_GR ] = gf100_gr_oclass;
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2015-01-14 15:30:09 +10:00
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
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2015-01-14 15:30:40 +10:00
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device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
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2015-01-14 15:30:22 +10:00
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device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
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2015-01-14 15:22:32 +10:00
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device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
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device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
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2015-01-14 15:24:57 +10:00
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device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
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2015-01-14 15:31:13 +10:00
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device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
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2012-07-06 07:36:43 +10:00
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break;
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case 0xc4:
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2012-07-27 08:28:20 +10:00
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device->cname = "GF104";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2015-01-14 15:02:59 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 15:04:16 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-26 00:26:38 +02:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 14:47:24 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2015-01-14 15:11:48 +10:00
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 14:48:16 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 15:08:21 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
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2015-01-14 14:40:22 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 14:52:58 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-10 04:10:28 +10:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 15:04:31 +10:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 15:09:19 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 14:35:35 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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2015-01-14 15:10:40 +10:00
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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2013-02-08 09:34:56 +10:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2015-01-14 15:27:54 +10:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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2015-01-14 15:28:47 +10:00
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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2015-01-14 15:32:15 +10:00
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device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
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2015-01-14 15:29:43 +10:00
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device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
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2015-01-14 15:30:09 +10:00
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
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2015-01-14 15:30:40 +10:00
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device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
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2015-01-14 15:30:22 +10:00
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device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
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2015-01-14 15:22:32 +10:00
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device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
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device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
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2015-01-14 15:24:57 +10:00
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device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
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2015-01-14 15:31:13 +10:00
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device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
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2012-07-06 07:36:43 +10:00
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break;
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case 0xc3:
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2012-07-27 08:28:20 +10:00
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device->cname = "GF106";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2015-01-14 15:02:59 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 15:04:16 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-26 00:26:38 +02:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 14:47:24 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2015-01-14 15:11:48 +10:00
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 14:48:16 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 15:08:21 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
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2015-01-14 14:40:22 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 14:52:58 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-10 04:10:28 +10:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 15:04:31 +10:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 15:09:19 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 14:35:35 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
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2015-01-14 15:10:40 +10:00
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device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
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2013-02-08 09:34:56 +10:00
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device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
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2015-01-14 15:27:54 +10:00
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device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
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2015-01-14 15:28:47 +10:00
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device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
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2015-01-14 15:32:15 +10:00
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device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
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2015-01-14 15:29:43 +10:00
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device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
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2015-01-14 15:30:09 +10:00
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device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
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2015-01-14 15:30:40 +10:00
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device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
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2015-01-14 15:30:22 +10:00
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device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
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2015-01-14 15:22:32 +10:00
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device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
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2015-01-14 15:24:57 +10:00
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device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
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2015-01-14 15:31:13 +10:00
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device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
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2012-07-06 07:36:43 +10:00
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break;
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case 0xce:
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2012-07-27 08:28:20 +10:00
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device->cname = "GF114";
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2015-01-14 15:35:00 +10:00
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device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
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2015-01-14 15:02:59 +10:00
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device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
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2015-01-14 15:04:16 +10:00
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device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
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2014-08-26 00:26:38 +02:00
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device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
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2015-01-14 14:47:24 +10:00
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device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
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2015-01-14 15:11:48 +10:00
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device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
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2012-07-22 16:41:26 +10:00
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device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
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2015-01-14 14:48:16 +10:00
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device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
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2015-01-14 15:08:21 +10:00
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device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
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2015-01-14 14:40:22 +10:00
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device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
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2012-07-11 16:08:25 +10:00
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device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
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2015-01-14 14:52:58 +10:00
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device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
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2014-08-10 04:10:28 +10:00
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device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
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2015-01-14 15:04:31 +10:00
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device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
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2013-12-23 00:39:47 +10:00
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device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
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2015-01-14 15:09:19 +10:00
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device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
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2015-01-14 14:35:35 +10:00
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device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2015-01-14 15:27:54 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
|
2015-01-14 15:32:15 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
2015-01-14 15:29:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
|
|
|
|
|
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xcf:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "GF116";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2014-08-26 00:26:38 +02:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-10 04:10:28 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 15:04:31 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 15:09:19 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 14:35:35 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2015-01-14 15:27:54 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
|
2015-01-14 15:32:15 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
2015-01-14 15:29:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = gf104_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xc1:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "GF108";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2014-08-26 00:26:38 +02:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-10 04:10:28 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 15:04:31 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 15:09:19 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 14:35:35 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2015-01-14 15:27:54 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
|
2015-01-14 15:32:15 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
2015-01-14 15:29:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = gf108_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xc8:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "GF110";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = g94_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = g94_i2c_oclass;
|
2014-08-26 00:26:38 +02:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = >215_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-10 04:10:28 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 15:04:31 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 15:09:19 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 14:35:35 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2015-01-14 15:27:54 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
|
2015-01-14 15:32:15 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
2015-01-14 15:29:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = gf110_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
|
|
|
|
|
device->oclass[NVDEV_ENGINE_CE1 ] = &gf100_ce1_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gt215_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
case 0xd9:
|
2012-07-27 08:28:20 +10:00
|
|
|
device->cname = "GF119";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
|
2015-01-14 15:04:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = gf110_i2c_oclass;
|
2014-08-26 00:26:38 +02:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
|
2012-07-22 16:41:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2012-07-11 16:08:25 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-10 04:10:28 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 15:04:31 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 15:09:19 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 14:35:35 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-14 15:10:40 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
|
2013-02-08 09:34:56 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
2015-01-14 15:27:54 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
|
2015-01-14 15:32:15 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
2015-01-14 15:29:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = gf119_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
|
2013-03-30 21:56:26 +10:00
|
|
|
break;
|
|
|
|
|
case 0xd7:
|
|
|
|
|
device->cname = "GF117";
|
2015-01-14 15:35:00 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nvkm_bios_oclass;
|
2015-01-14 15:02:59 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_GPIO ] = gf110_gpio_oclass;
|
2014-06-18 15:46:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
|
2014-08-26 00:26:38 +02:00
|
|
|
device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
|
2015-01-14 14:47:24 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
|
2015-01-14 15:11:48 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_THERM ] = &gf110_therm_oclass;
|
2013-03-30 21:56:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
|
2015-01-14 14:48:16 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
|
2015-01-14 15:08:21 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
|
2015-01-14 14:40:22 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
|
2013-03-30 21:56:26 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
|
2015-01-14 14:52:58 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_FB ] = gf100_fb_oclass;
|
2014-08-10 04:10:28 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
|
2015-01-14 15:04:31 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
2013-12-23 00:39:47 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
2015-01-14 15:09:19 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
2015-01-14 14:35:35 +10:00
|
|
|
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
2015-01-14 15:27:54 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
2015-01-14 15:28:47 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
|
2015-01-14 15:32:15 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
2015-01-14 15:29:43 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_GR ] = gf117_gr_oclass;
|
2015-01-14 15:30:09 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPDEC ] = &gf100_mspdec_oclass;
|
2015-01-14 15:30:40 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSVLD ] = &gf100_msvld_oclass;
|
2015-01-14 15:30:22 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_MSPPP ] = &gf100_msppp_oclass;
|
2015-01-14 15:22:32 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_CE0 ] = &gf100_ce0_oclass;
|
2015-01-14 15:24:57 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_DISP ] = gf110_disp_oclass;
|
2015-01-14 15:31:13 +10:00
|
|
|
device->oclass[NVDEV_ENGINE_PM ] = &gf100_pm_oclass;
|
2012-07-06 07:36:43 +10:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
nv_fatal(device, "unknown Fermi chipset\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
2015-01-14 15:35:00 +10:00
|
|
|
}
|