2007-06-04 06:45:38 +01:00
										 
									 
								 
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								/*
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								 * arch/arm/mach-at91/include/mach/at91x40.h
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								 *
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								 * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
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								 *
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								 * This program is free software; you can redistribute it and/or modify
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								 * it under the terms of the GNU General Public License as published by
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								 * the Free Software Foundation; either version 2 of the License, or
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								 * (at your option) any later version.
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								 */
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								#ifndef AT91X40_H
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								#define AT91X40_H
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								/*
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								 *	IRQ list.
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								 */
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								#define AT91X40_ID_USART0	2	/* USART port 0 */
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								#define AT91X40_ID_USART1	3	/* USART port 1 */
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								#define AT91X40_ID_TC0		4	/* Timer/Counter 0 */
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								#define AT91X40_ID_TC1		5	/* Timer/Counter 1*/
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								#define AT91X40_ID_TC2		6	/* Timer/Counter 2*/
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								#define AT91X40_ID_WD		7	/* Watchdog? */
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								#define AT91X40_ID_PIOA		8	/* Parallel IO Controller A */
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								#define AT91X40_ID_IRQ0		16	/* External IRQ 0 */
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								#define AT91X40_ID_IRQ1		17	/* External IRQ 1 */
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								#define AT91X40_ID_IRQ2		18	/* External IRQ 2 */
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								/*
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											2012-02-05 20:35:39 +08:00
										 
									 
								 
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								 * System Peripherals
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								 */
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								#define AT91_BASE_SYS	0xffc00000
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								#define AT91_EBI	0xffe00000	/* External Bus Interface */
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								#define AT91_SF		0xfff00000	/* Special Function */
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								#define AT91_USART1	0xfffcc000	/* USART 1 */
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								#define AT91_USART0	0xfffd0000	/* USART 0 */
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								#define AT91_TC		0xfffe0000	/* Timer Counter */
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								#define AT91_PIOA	0xffff0000	/* PIO Controller A */
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								#define AT91_PS		0xffff4000	/* Power Save */
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								#define AT91_WD		0xffff8000	/* Watchdog Timer */
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								/*
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								 * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
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								 * But it does have a chip identify register and extension ID, so define at
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								 * least these here.
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								 */
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								#define AT91_DBGU_CIDR	(AT91_SF + 0)	/* CIDR in PS segment */
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								#define AT91_DBGU_EXID	(AT91_SF + 4)	/* EXID in PS segment */
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											2010-09-21 20:39:40 +10:00
										 
									 
								 
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								/*
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								 * Support defines for the simple Power Controller module.
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								 */
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								#define	AT91_PS_CR	(AT91_PS + 0)	/* PS Control register */
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								#define	AT91_PS_CR_CPU	(1 << 0)	/* CPU clock disable bit */
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								#endif /* AT91X40_H */
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