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linux-pinenote/drivers/clk/at91/pmc.c

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clk: at91: add PMC base support This patch adds at91 PMC (Power Management Controller) base support. All at91 clocks managed by the PMC unit will use this framework. This framework provides the following fonctionalities: - define a new struct at91_pmc to hide PMC internals (lock, PMC memory mapping, irq domain, ...) - read/write helper functions (pmc_read/write) to access PMC registers - lock/unlock helper functions (pmc_lock/unlock) to lock/unlock access to pmc registers - a new irq domain and its associated irq chip to request PMC specific interrupts (useful for clk prepare callbacks) The PMC unit is declared as a dt clk provider (CLK_OF_DECLARE), and every clk using this framework will declare a table of of_at91_clk_init_cb_t and add it to the pmc_clk_ids table. When the pmc dt clock setup function is called (by of_clk_init function), it triggers the registration of every supported child clk (those matching the definitions in pmc_clk_ids). This patch copies at91_pmc_base (memory mapping) and at91sam9_idle (function) from arch/arm/mach-at91/clock.c (which is not compiled if COMMON_CLK_AT91 is enabled). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-12-02 15:07:02 +01:00
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/clk/at91_pmc.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/irqdomain.h>
#include <linux/of_irq.h>
#include <asm/proc-fns.h>
#include "pmc.h"
void __iomem *at91_pmc_base;
EXPORT_SYMBOL_GPL(at91_pmc_base);
void at91sam9_idle(void)
{
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
}
int of_at91_get_clk_range(struct device_node *np, const char *propname,
struct clk_range *range)
{
u32 min, max;
int ret;
ret = of_property_read_u32_index(np, propname, 0, &min);
if (ret)
return ret;
ret = of_property_read_u32_index(np, propname, 1, &max);
if (ret)
return ret;
if (range) {
range->min = min;
range->max = max;
}
return 0;
}
EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
static void pmc_irq_mask(struct irq_data *d)
{
struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
pmc_write(pmc, AT91_PMC_IDR, 1 << d->hwirq);
}
static void pmc_irq_unmask(struct irq_data *d)
{
struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
pmc_write(pmc, AT91_PMC_IER, 1 << d->hwirq);
}
static int pmc_irq_set_type(struct irq_data *d, unsigned type)
{
if (type != IRQ_TYPE_LEVEL_HIGH) {
pr_warn("PMC: type not supported (support only IRQ_TYPE_LEVEL_HIGH type)\n");
return -EINVAL;
}
return 0;
}
static struct irq_chip pmc_irq = {
.name = "PMC",
.irq_disable = pmc_irq_mask,
.irq_mask = pmc_irq_mask,
.irq_unmask = pmc_irq_unmask,
.irq_set_type = pmc_irq_set_type,
};
static struct lock_class_key pmc_lock_class;
static int pmc_irq_map(struct irq_domain *h, unsigned int virq,
irq_hw_number_t hw)
{
struct at91_pmc *pmc = h->host_data;
irq_set_lockdep_class(virq, &pmc_lock_class);
irq_set_chip_and_handler(virq, &pmc_irq,
handle_level_irq);
set_irq_flags(virq, IRQF_VALID);
irq_set_chip_data(virq, pmc);
return 0;
}
static int pmc_irq_domain_xlate(struct irq_domain *d,
struct device_node *ctrlr,
const u32 *intspec, unsigned int intsize,
irq_hw_number_t *out_hwirq,
unsigned int *out_type)
{
struct at91_pmc *pmc = d->host_data;
const struct at91_pmc_caps *caps = pmc->caps;
if (WARN_ON(intsize < 1))
return -EINVAL;
*out_hwirq = intspec[0];
if (!(caps->available_irqs & (1 << *out_hwirq)))
return -EINVAL;
*out_type = IRQ_TYPE_LEVEL_HIGH;
return 0;
}
static struct irq_domain_ops pmc_irq_ops = {
.map = pmc_irq_map,
.xlate = pmc_irq_domain_xlate,
};
static irqreturn_t pmc_irq_handler(int irq, void *data)
{
struct at91_pmc *pmc = (struct at91_pmc *)data;
unsigned long sr;
int n;
sr = pmc_read(pmc, AT91_PMC_SR) & pmc_read(pmc, AT91_PMC_IMR);
if (!sr)
return IRQ_NONE;
for_each_set_bit(n, &sr, BITS_PER_LONG)
generic_handle_irq(irq_find_mapping(pmc->irqdomain, n));
return IRQ_HANDLED;
}
static const struct at91_pmc_caps at91rm9200_caps = {
.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
AT91_PMC_PCK3RDY,
};
static const struct at91_pmc_caps at91sam9260_caps = {
.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
AT91_PMC_PCK1RDY,
};
static const struct at91_pmc_caps at91sam9g45_caps = {
.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
AT91_PMC_PCK1RDY,
};
static const struct at91_pmc_caps at91sam9n12_caps = {
.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
};
static const struct at91_pmc_caps at91sam9x5_caps = {
.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
};
static const struct at91_pmc_caps sama5d3_caps = {
.available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS |
AT91_PMC_CFDEV,
};
static struct at91_pmc *__init at91_pmc_init(struct device_node *np,
void __iomem *regbase, int virq,
const struct at91_pmc_caps *caps)
{
struct at91_pmc *pmc;
if (!regbase || !virq || !caps)
return NULL;
at91_pmc_base = regbase;
pmc = kzalloc(sizeof(*pmc), GFP_KERNEL);
if (!pmc)
return NULL;
spin_lock_init(&pmc->lock);
pmc->regbase = regbase;
pmc->virq = virq;
pmc->caps = caps;
pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc);
if (!pmc->irqdomain)
goto out_free_pmc;
pmc_write(pmc, AT91_PMC_IDR, 0xffffffff);
if (request_irq(pmc->virq, pmc_irq_handler, IRQF_SHARED, "pmc", pmc))
goto out_remove_irqdomain;
return pmc;
out_remove_irqdomain:
irq_domain_remove(pmc->irqdomain);
out_free_pmc:
kfree(pmc);
return NULL;
}
clk: at91: fix pmc_clk_ids data type attriubte Fix pmc_clk_ids data type attribute (__initdata -> __initconst). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Reported-by: Fengguang Wu <fengguang.wu@intel.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-12-16 22:25:27 +01:00
static const struct of_device_id pmc_clk_ids[] __initconst = {
clk: at91: add slow clks driver AT91 slow clk is a clk multiplexer. In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can choose among 2 sources: an internal RC oscillator circuit and an oscillator using an external crystal. In other Socs (sam9260 family) the multiplexer source is hardcoded with the OSCSEL signal. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-05-07 18:02:15 +02:00
/* Slow oscillator */
{
.compatible = "atmel,at91sam9260-clk-slow",
.data = of_at91sam9260_clk_slow_setup,
},
clk: at91: add PMC main clock This patch adds new at91 main oscillator clock implementation using common clk framework. If rate is not provided during clock registration it is calculated using the slow clock (main clk parent in this case) rate and MCFR register. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 10:44:49 +02:00
/* Main clock */
clk: at91: rework main clk implementation AT91 main clk is a clk multiplexer and not a simple fixed rate clk as currently implemented. In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can choose among 2 sources: an internal RC oscillator circuit and an oscillator using an external crystal. In other Socs (sam9260, rm9200 families) the multiplexer source is hardcoded to the external crystal oscillator. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-05-07 18:00:08 +02:00
{
.compatible = "atmel,at91rm9200-clk-main-osc",
.data = of_at91rm9200_clk_main_osc_setup,
},
{
.compatible = "atmel,at91sam9x5-clk-main-rc-osc",
.data = of_at91sam9x5_clk_main_rc_osc_setup,
},
clk: at91: add PMC main clock This patch adds new at91 main oscillator clock implementation using common clk framework. If rate is not provided during clock registration it is calculated using the slow clock (main clk parent in this case) rate and MCFR register. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 10:44:49 +02:00
{
.compatible = "atmel,at91rm9200-clk-main",
.data = of_at91rm9200_clk_main_setup,
},
clk: at91: rework main clk implementation AT91 main clk is a clk multiplexer and not a simple fixed rate clk as currently implemented. In some SoCs (sam9x5, sama5, sam9g45 families) this multiplexer can choose among 2 sources: an internal RC oscillator circuit and an oscillator using an external crystal. In other Socs (sam9260, rm9200 families) the multiplexer source is hardcoded to the external crystal oscillator. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-05-07 18:00:08 +02:00
{
.compatible = "atmel,at91sam9x5-clk-main",
.data = of_at91sam9x5_clk_main_setup,
},
clk: at91: add PMC pll clocks This patch adds new at91 pll clock implementation using common clk framework. The pll clock layout describe the PLLX register layout. There are four pll clock layouts: - at91rm9200 - at91sam9g20 - at91sam9g45 - sama5d3 PLL clocks are given characteristics: - min/max clock source rate - ranges of valid clock output rates - values to set in out and icpll fields for each supported output range These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 10:48:26 +02:00
/* PLL clocks */
{
.compatible = "atmel,at91rm9200-clk-pll",
.data = of_at91rm9200_clk_pll_setup,
},
{
.compatible = "atmel,at91sam9g45-clk-pll",
.data = of_at91sam9g45_clk_pll_setup,
},
{
.compatible = "atmel,at91sam9g20-clk-pllb",
.data = of_at91sam9g20_clk_pllb_setup,
},
{
.compatible = "atmel,sama5d3-clk-pll",
.data = of_sama5d3_clk_pll_setup,
},
{
.compatible = "atmel,at91sam9x5-clk-plldiv",
.data = of_at91sam9x5_clk_plldiv_setup,
},
clk: at91: add PMC master clock This patch adds new at91 master clock implementation using common clk framework. The master clock layout describe the MCKR register layout. There are 2 master clock layouts: - at91rm9200 - at91sam9x5 Master clocks are given characteristics: - min/max clock output rate These characteristics are checked during rate change to avoid over/underclocking. These characteristics are described in atmel's SoC datasheet in "Electrical Characteristics" paragraph. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 10:51:23 +02:00
/* Master clock */
{
.compatible = "atmel,at91rm9200-clk-master",
.data = of_at91rm9200_clk_master_setup,
},
{
.compatible = "atmel,at91sam9x5-clk-master",
.data = of_at91sam9x5_clk_master_setup,
},
clk: at91: add PMC system clocks This patch adds new at91 system clock implementation using common clk framework. Some peripherals need to enable a "system" clock in order to work properly. Each system clock is given an id based on the bit position in SCER/SCDR registers. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 11:41:41 +02:00
/* System clocks */
{
.compatible = "atmel,at91rm9200-clk-system",
.data = of_at91rm9200_clk_sys_setup,
},
clk: at91: add PMC peripheral clocks This patch adds new at91 peripheral clock implementation using common clk framework. Almost all peripherals provided by at91 SoCs need a clock to work properly. This clock is enabled/disabled using PCER/PCDR resgisters. Each peripheral is given an id (see atmel's datasheets) which is used to define and reference peripheral clocks. Some new SoCs (at91sam9x5 and sama5d3) provide a new register (PCR) where you can configure the peripheral clock as a division of the master clock. This will help reducing the peripherals power comsumption. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 11:44:36 +02:00
/* Peripheral clocks */
{
.compatible = "atmel,at91rm9200-clk-peripheral",
.data = of_at91rm9200_clk_periph_setup,
},
{
.compatible = "atmel,at91sam9x5-clk-peripheral",
.data = of_at91sam9x5_clk_periph_setup,
},
clk: at91: add PMC programmable clocks This patch adds new at91 programmable clocks implementation using common clk framework. A programmable clock is a clock which can be exported on a given pin to clock external devices. Each programmable clock is given an id (from 0 to 8). The number of available programmable clocks depends on the SoC you're using. Programmable clock driver only implements the clock setting (clock rate and parent setting). It must be chained to a system clock in order to enable/disable the generated clock. The PCKX pins used to output the clock signals must be assigned to the appropriate peripheral (see atmel's datasheets). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 11:57:04 +02:00
/* Programmable clocks */
{
.compatible = "atmel,at91rm9200-clk-programmable",
.data = of_at91rm9200_clk_prog_setup,
},
{
.compatible = "atmel,at91sam9g45-clk-programmable",
.data = of_at91sam9g45_clk_prog_setup,
},
{
.compatible = "atmel,at91sam9x5-clk-programmable",
.data = of_at91sam9x5_clk_prog_setup,
},
clk: at91: add PMC utmi clock This adds new at91 utmi clock implementation using common clk framework. This clock is a pll with a fixed factor (x40). It is used as a source for usb clock. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 12:22:06 +02:00
/* UTMI clock */
#if defined(CONFIG_HAVE_AT91_UTMI)
{
.compatible = "atmel,at91sam9x5-clk-utmi",
.data = of_at91sam9x5_clk_utmi_setup,
},
clk: at91: add PMC usb clock This patch adds new at91 usb clock implementation using common clk framework. This clock is used to clock usb ports (ohci, ehci and udc). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-17 18:55:41 +02:00
#endif
/* USB clock */
#if defined(CONFIG_HAVE_AT91_USB_CLK)
{
.compatible = "atmel,at91rm9200-clk-usb",
.data = of_at91rm9200_clk_usb_setup,
},
{
.compatible = "atmel,at91sam9x5-clk-usb",
.data = of_at91sam9x5_clk_usb_setup,
},
{
.compatible = "atmel,at91sam9n12-clk-usb",
.data = of_at91sam9n12_clk_usb_setup,
},
clk: at91: add PMC smd clock This patch adds at91 smd (Soft Modem) clock implementation using common clk framework. Not used by any driver right now. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 13:27:06 +02:00
#endif
/* SMD clock */
#if defined(CONFIG_HAVE_AT91_SMD)
{
.compatible = "atmel,at91sam9x5-clk-smd",
.data = of_at91sam9x5_clk_smd_setup,
},
clk: at91: add a driver for the h32mx clock Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix interconnect (h32mx) has a clock that can be setup at the half of the h64mx clock (which is mck). The h32mx clock can not exceed 90 MHz. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-09-15 18:15:53 +02:00
#endif
#if defined(CONFIG_HAVE_AT91_H32MX)
{
.compatible = "atmel,sama5d4-clk-h32mx",
.data = of_sama5d4_clk_h32mx_setup,
},
clk: at91: add PMC programmable clocks This patch adds new at91 programmable clocks implementation using common clk framework. A programmable clock is a clock which can be exported on a given pin to clock external devices. Each programmable clock is given an id (from 0 to 8). The number of available programmable clocks depends on the SoC you're using. Programmable clock driver only implements the clock setting (clock rate and parent setting). It must be chained to a system clock in order to enable/disable the generated clock. The PCKX pins used to output the clock signals must be assigned to the appropriate peripheral (see atmel's datasheets). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-10-11 11:57:04 +02:00
#endif
clk: at91: add PMC base support This patch adds at91 PMC (Power Management Controller) base support. All at91 clocks managed by the PMC unit will use this framework. This framework provides the following fonctionalities: - define a new struct at91_pmc to hide PMC internals (lock, PMC memory mapping, irq domain, ...) - read/write helper functions (pmc_read/write) to access PMC registers - lock/unlock helper functions (pmc_lock/unlock) to lock/unlock access to pmc registers - a new irq domain and its associated irq chip to request PMC specific interrupts (useful for clk prepare callbacks) The PMC unit is declared as a dt clk provider (CLK_OF_DECLARE), and every clk using this framework will declare a table of of_at91_clk_init_cb_t and add it to the pmc_clk_ids table. When the pmc dt clock setup function is called (by of_clk_init function), it triggers the registration of every supported child clk (those matching the definitions in pmc_clk_ids). This patch copies at91_pmc_base (memory mapping) and at91sam9_idle (function) from arch/arm/mach-at91/clock.c (which is not compiled if COMMON_CLK_AT91 is enabled). Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2013-12-02 15:07:02 +01:00
{ /*sentinel*/ }
};
static void __init of_at91_pmc_setup(struct device_node *np,
const struct at91_pmc_caps *caps)
{
struct at91_pmc *pmc;
struct device_node *childnp;
void (*clk_setup)(struct device_node *, struct at91_pmc *);
const struct of_device_id *clk_id;
void __iomem *regbase = of_iomap(np, 0);
int virq;
if (!regbase)
return;
virq = irq_of_parse_and_map(np, 0);
if (!virq)
return;
pmc = at91_pmc_init(np, regbase, virq, caps);
if (!pmc)
return;
for_each_child_of_node(np, childnp) {
clk_id = of_match_node(pmc_clk_ids, childnp);
if (!clk_id)
continue;
clk_setup = clk_id->data;
clk_setup(childnp, pmc);
}
}
static void __init of_at91rm9200_pmc_setup(struct device_node *np)
{
of_at91_pmc_setup(np, &at91rm9200_caps);
}
CLK_OF_DECLARE(at91rm9200_clk_pmc, "atmel,at91rm9200-pmc",
of_at91rm9200_pmc_setup);
static void __init of_at91sam9260_pmc_setup(struct device_node *np)
{
of_at91_pmc_setup(np, &at91sam9260_caps);
}
CLK_OF_DECLARE(at91sam9260_clk_pmc, "atmel,at91sam9260-pmc",
of_at91sam9260_pmc_setup);
static void __init of_at91sam9g45_pmc_setup(struct device_node *np)
{
of_at91_pmc_setup(np, &at91sam9g45_caps);
}
CLK_OF_DECLARE(at91sam9g45_clk_pmc, "atmel,at91sam9g45-pmc",
of_at91sam9g45_pmc_setup);
static void __init of_at91sam9n12_pmc_setup(struct device_node *np)
{
of_at91_pmc_setup(np, &at91sam9n12_caps);
}
CLK_OF_DECLARE(at91sam9n12_clk_pmc, "atmel,at91sam9n12-pmc",
of_at91sam9n12_pmc_setup);
static void __init of_at91sam9x5_pmc_setup(struct device_node *np)
{
of_at91_pmc_setup(np, &at91sam9x5_caps);
}
CLK_OF_DECLARE(at91sam9x5_clk_pmc, "atmel,at91sam9x5-pmc",
of_at91sam9x5_pmc_setup);
static void __init of_sama5d3_pmc_setup(struct device_node *np)
{
of_at91_pmc_setup(np, &sama5d3_caps);
}
CLK_OF_DECLARE(sama5d3_clk_pmc, "atmel,sama5d3-pmc",
of_sama5d3_pmc_setup);
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