2011-11-10 12:03:26 +00:00
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/*
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* NetLogic DB1300 board constants
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*/
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#ifndef _DB1300_H_
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#define _DB1300_H_
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/* FPGA (external mux) interrupt sources */
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#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
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#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
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#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
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#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
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#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
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#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
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#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
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#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
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#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
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#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
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#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
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#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
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#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
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#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
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#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
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2013-01-22 12:59:30 +01:00
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#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
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2011-11-10 12:03:26 +00:00
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#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
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/* SMSC9210 CS */
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#define DB1300_ETH_PHYS_ADDR 0x19000000
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#define DB1300_ETH_PHYS_END 0x197fffff
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/* ATA CS */
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#define DB1300_IDE_PHYS_ADDR 0x18800000
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#define DB1300_IDE_REG_SHIFT 5
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#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
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/* NAND CS */
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#define DB1300_NAND_PHYS_ADDR 0x20000000
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#define DB1300_NAND_PHYS_END 0x20000fff
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#endif /* _DB1300_H_ */
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