65 lines
		
	
	
	
		
			2.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
		
		
			
		
	
	
			65 lines
		
	
	
	
		
			2.4 KiB
			
		
	
	
	
		
			C
		
	
	
	
	
	
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								/*
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								 * include/video/epson13xx.h -- Epson 13xx frame buffer
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								 *
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								 * Copyright (C) Hewlett-Packard Company.  All rights reserved.
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								 *
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								 * Written by Christopher Hoover <ch@hpl.hp.com>
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								 *
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								 */
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								#ifndef _EPSON13XX_H_
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								#define _EPSON13XX_H_
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								#define REG_REVISION_CODE              0x00
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								#define REG_MEMORY_CONFIG              0x01
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								#define REG_PANEL_TYPE                 0x02
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								#define REG_MOD_RATE                   0x03
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								#define REG_HORZ_DISP_WIDTH            0x04
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								#define REG_HORZ_NONDISP_PERIOD        0x05
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								#define REG_HRTC_START_POSITION        0x06
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								#define REG_HRTC_PULSE_WIDTH           0x07
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								#define REG_VERT_DISP_HEIGHT0          0x08
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								#define REG_VERT_DISP_HEIGHT1          0x09
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								#define REG_VERT_NONDISP_PERIOD        0x0A
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								#define REG_VRTC_START_POSITION        0x0B
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								#define REG_VRTC_PULSE_WIDTH           0x0C
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								#define REG_DISPLAY_MODE               0x0D
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								#define REG_SCRN1_LINE_COMPARE0        0x0E
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								#define REG_SCRN1_LINE_COMPARE1        0x0F
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								#define REG_SCRN1_DISP_START_ADDR0     0x10
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								#define REG_SCRN1_DISP_START_ADDR1     0x11
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								#define REG_SCRN1_DISP_START_ADDR2     0x12
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								#define REG_SCRN2_DISP_START_ADDR0     0x13
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								#define REG_SCRN2_DISP_START_ADDR1     0x14
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								#define REG_SCRN2_DISP_START_ADDR2     0x15
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								#define REG_MEM_ADDR_OFFSET0           0x16
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								#define REG_MEM_ADDR_OFFSET1           0x17
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								#define REG_PIXEL_PANNING              0x18
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								#define REG_CLOCK_CONFIG               0x19
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								#define REG_POWER_SAVE_CONFIG          0x1A
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								#define REG_MISC                       0x1B
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								#define REG_MD_CONFIG_READBACK0        0x1C
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								#define REG_MD_CONFIG_READBACK1        0x1D
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								#define REG_GPIO_CONFIG0               0x1E
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								#define REG_GPIO_CONFIG1               0x1F
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								#define REG_GPIO_CONTROL0              0x20
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								#define REG_GPIO_CONTROL1              0x21
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								#define REG_PERF_ENHANCEMENT0          0x22
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								#define REG_PERF_ENHANCEMENT1          0x23
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								#define REG_LUT_ADDR                   0x24
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								#define REG_RESERVED_1                 0x25
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								#define REG_LUT_DATA                   0x26
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								#define REG_INK_CURSOR_CONTROL         0x27
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								#define REG_CURSOR_X_POSITION0         0x28
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								#define REG_CURSOR_X_POSITION1         0x29
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								#define REG_CURSOR_Y_POSITION0         0x2A
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								#define REG_CURSOR_Y_POSITION1         0x2B
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								#define REG_INK_CURSOR_COLOR0_0        0x2C
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								#define REG_INK_CURSOR_COLOR0_1        0x2D
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								#define REG_INK_CURSOR_COLOR1_0        0x2E
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								#define REG_INK_CURSOR_COLOR1_1        0x2F
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								#define REG_INK_CURSOR_START_ADDR      0x30
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								#define REG_ALTERNATE_FRM              0x31
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								#endif
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