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											2008-04-29 01:00:31 -07:00
										 |  |  | 			DMA attributes | 
					
						
							|  |  |  | 			============== | 
					
						
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							|  |  |  | This document describes the semantics of the DMA attributes that are | 
					
						
							|  |  |  | defined in linux/dma-attrs.h. | 
					
						
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							|  |  |  | DMA_ATTR_WRITE_BARRIER | 
					
						
							|  |  |  | ---------------------- | 
					
						
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							|  |  |  | DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA.  DMA | 
					
						
							|  |  |  | to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces | 
					
						
							|  |  |  | all pending DMA writes to complete, and thus provides a mechanism to | 
					
						
							|  |  |  | strictly order DMA from a device across all intervening busses and | 
					
						
							|  |  |  | bridges.  This barrier is not specific to a particular type of | 
					
						
							|  |  |  | interconnect, it applies to the system as a whole, and so its | 
					
						
							|  |  |  | implementation must account for the idiosyncracies of the system all | 
					
						
							|  |  |  | the way from the DMA device to memory. | 
					
						
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							|  |  |  | As an example of a situation where DMA_ATTR_WRITE_BARRIER would be | 
					
						
							|  |  |  | useful, suppose that a device does a DMA write to indicate that data is | 
					
						
							|  |  |  | ready and available in memory.  The DMA of the "completion indication" | 
					
						
							|  |  |  | could race with data DMA.  Mapping the memory used for completion | 
					
						
							|  |  |  | indications with DMA_ATTR_WRITE_BARRIER would prevent the race. | 
					
						
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											2008-07-18 23:03:34 +10:00
										 |  |  | DMA_ATTR_WEAK_ORDERING | 
					
						
							|  |  |  | ---------------------- | 
					
						
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							|  |  |  | DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping | 
					
						
							|  |  |  | may be weakly ordered, that is that reads and writes may pass each other. | 
					
						
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							|  |  |  | Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, | 
					
						
							|  |  |  | those that do not will simply ignore the attribute and exhibit default | 
					
						
							|  |  |  | behavior. |