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											2007-10-15 23:28:20 +02:00
										 |  |  | #ifndef _ARCH_X86_CACHE_H
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							|  |  |  | #define _ARCH_X86_CACHE_H
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							|  |  |  | /* L1 cache line size */ | 
					
						
							|  |  |  | #define L1_CACHE_SHIFT	(CONFIG_X86_L1_CACHE_SHIFT)
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							|  |  |  | #define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
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							|  |  |  | #define __read_mostly __attribute__((__section__(".data.read_mostly")))
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							|  |  |  | #ifdef CONFIG_X86_VSMP
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							|  |  |  | /* vSMP Internode cacheline shift */ | 
					
						
							|  |  |  | #define INTERNODE_CACHE_SHIFT (12)
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							|  |  |  | #ifdef CONFIG_SMP
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							|  |  |  | #define __cacheline_aligned_in_smp					\
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							|  |  |  | 	__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))	\ | 
					
						
							|  |  |  | 	__attribute__((__section__(".data.page_aligned"))) | 
					
						
							|  |  |  | #endif
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							|  |  |  | #endif
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											2007-10-11 11:20:03 +02:00
										 |  |  | #endif
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