| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  | /*
 | 
					
						
							| 
									
										
										
										
											2008-08-05 16:14:15 +01:00
										 |  |  |  * arch/arm/mach-sa1100/include/mach/memory.h | 
					
						
							| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  |  * | 
					
						
							| 
									
										
										
										
											2009-09-14 03:25:28 -04:00
										 |  |  |  * Copyright (C) 1999-2000 Nicolas Pitre <nico@fluxnic.net> | 
					
						
							| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  |  */ | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #ifndef __ASM_ARCH_MEMORY_H
 | 
					
						
							|  |  |  | #define __ASM_ARCH_MEMORY_H
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | #include <asm/sizes.h>
 | 
					
						
							|  |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							|  |  |  |  * Physical DRAM offset is 0xc0000000 on the SA1100 | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2011-01-04 18:07:14 +00:00
										 |  |  | #define PLAT_PHYS_OFFSET	UL(0xc0000000)
 | 
					
						
							| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  | 
 | 
					
						
							|  |  |  | /*
 | 
					
						
							| 
									
										
										
										
											2008-10-01 21:03:21 +01:00
										 |  |  |  * Because of the wide memory address space between physical RAM banks on the | 
					
						
							|  |  |  |  * SA1100, it's much convenient to use Linux's SparseMEM support to implement | 
					
						
							|  |  |  |  * our memory map representation.  Assuming all memory nodes have equal access | 
					
						
							| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  |  * characteristics, we then have generic discontiguous memory support. | 
					
						
							|  |  |  |  * | 
					
						
							| 
									
										
										
										
											2008-10-01 21:03:21 +01:00
										 |  |  |  * The sparsemem banks are matched with the physical memory bank addresses | 
					
						
							|  |  |  |  * which are incidentally the same as virtual addresses. | 
					
						
							| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  |  *  | 
					
						
							|  |  |  |  * 	node 0:  0xc0000000 - 0xc7ffffff | 
					
						
							|  |  |  |  * 	node 1:  0xc8000000 - 0xcfffffff | 
					
						
							|  |  |  |  * 	node 2:  0xd0000000 - 0xd7ffffff | 
					
						
							|  |  |  |  * 	node 3:  0xd8000000 - 0xdfffffff | 
					
						
							|  |  |  |  */ | 
					
						
							| 
									
										
										
										
											2008-10-01 21:03:21 +01:00
										 |  |  | #define MAX_PHYSMEM_BITS	32
 | 
					
						
							|  |  |  | #define SECTION_SIZE_BITS	27
 | 
					
						
							| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  | 
 | 
					
						
							| 
									
										
										
										
											2006-04-04 21:47:43 +01:00
										 |  |  | /*
 | 
					
						
							|  |  |  |  * Cache flushing area - SA1100 zero bank | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define FLUSH_BASE_PHYS		0xe0000000
 | 
					
						
							|  |  |  | #define FLUSH_BASE		0xf5000000
 | 
					
						
							|  |  |  | #define FLUSH_BASE_MINICACHE	0xf5100000
 | 
					
						
							|  |  |  | 
 | 
					
						
							| 
									
										
										
										
											2005-04-16 15:20:36 -07:00
										 |  |  | #endif
 |