2007-09-25 17:57:13 -07:00
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/*
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2009-11-08 16:39:55 +01:00
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Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
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2007-09-25 17:57:13 -07:00
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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2013-12-06 03:32:11 -08:00
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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2007-09-25 17:57:13 -07:00
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*/
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/*
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Module: rt2400pci
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Abstract: Data structures and registers for the rt2400pci module.
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Supported chipsets: RT2460.
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*/
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#ifndef RT2400PCI_H
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#define RT2400PCI_H
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/*
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* RF chip defines.
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*/
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#define RF2420 0x0000
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#define RF2421 0x0001
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/*
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* Signal information.
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tree-wide: fix assorted typos all over the place
That is "success", "unknown", "through", "performance", "[re|un]mapping"
, "access", "default", "reasonable", "[con]currently", "temperature"
, "channel", "[un]used", "application", "example","hierarchy", "therefore"
, "[over|under]flow", "contiguous", "threshold", "enough" and others.
Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2009-11-14 13:09:05 -02:00
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* Default offset is required for RSSI <-> dBm conversion.
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2007-09-25 17:57:13 -07:00
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*/
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#define DEFAULT_RSSI_OFFSET 100
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/*
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* Register layout information.
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*/
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#define CSR_REG_BASE 0x0000
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#define CSR_REG_SIZE 0x014c
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#define EEPROM_BASE 0x0000
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#define EEPROM_SIZE 0x0100
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2008-10-29 19:41:03 +01:00
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#define BBP_BASE 0x0000
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2007-09-25 17:57:13 -07:00
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#define BBP_SIZE 0x0020
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2009-02-15 17:42:48 +01:00
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#define RF_BASE 0x0004
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#define RF_SIZE 0x000c
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2007-09-25 17:57:13 -07:00
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2008-05-10 13:43:33 +02:00
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/*
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* Number of TX queues.
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*/
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#define NUM_TX_QUEUES 2
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2007-09-25 17:57:13 -07:00
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/*
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* Control/Status Registers(CSR).
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* Some values are set in TU, whereas 1 TU == 1024 us.
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*/
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/*
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* CSR0: ASIC revision number.
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*/
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#define CSR0 0x0000
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2010-02-13 20:55:49 +01:00
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#define CSR0_REVISION FIELD32(0x0000ffff)
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2007-09-25 17:57:13 -07:00
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/*
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* CSR1: System control register.
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* SOFT_RESET: Software reset, 1: reset, 0: normal.
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* BBP_RESET: Hardware reset, 1: reset, 0, release.
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* HOST_READY: Host ready after initialization.
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*/
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#define CSR1 0x0004
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#define CSR1_SOFT_RESET FIELD32(0x00000001)
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#define CSR1_BBP_RESET FIELD32(0x00000002)
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#define CSR1_HOST_READY FIELD32(0x00000004)
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/*
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* CSR2: System admin status register (invalid).
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*/
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#define CSR2 0x0008
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/*
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* CSR3: STA MAC address register 0.
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*/
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#define CSR3 0x000c
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#define CSR3_BYTE0 FIELD32(0x000000ff)
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#define CSR3_BYTE1 FIELD32(0x0000ff00)
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#define CSR3_BYTE2 FIELD32(0x00ff0000)
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#define CSR3_BYTE3 FIELD32(0xff000000)
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/*
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* CSR4: STA MAC address register 1.
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*/
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#define CSR4 0x0010
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#define CSR4_BYTE4 FIELD32(0x000000ff)
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#define CSR4_BYTE5 FIELD32(0x0000ff00)
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/*
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* CSR5: BSSID register 0.
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*/
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#define CSR5 0x0014
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#define CSR5_BYTE0 FIELD32(0x000000ff)
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#define CSR5_BYTE1 FIELD32(0x0000ff00)
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#define CSR5_BYTE2 FIELD32(0x00ff0000)
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#define CSR5_BYTE3 FIELD32(0xff000000)
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/*
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* CSR6: BSSID register 1.
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*/
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#define CSR6 0x0018
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#define CSR6_BYTE4 FIELD32(0x000000ff)
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#define CSR6_BYTE5 FIELD32(0x0000ff00)
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/*
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* CSR7: Interrupt source register.
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* Write 1 to clear interrupt.
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* TBCN_EXPIRE: Beacon timer expired interrupt.
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* TWAKE_EXPIRE: Wakeup timer expired interrupt.
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* TATIMW_EXPIRE: Timer of atim window expired interrupt.
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* TXDONE_TXRING: Tx ring transmit done interrupt.
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* TXDONE_ATIMRING: Atim ring transmit done interrupt.
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* TXDONE_PRIORING: Priority ring transmit done interrupt.
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* RXDONE: Receive done interrupt.
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*/
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#define CSR7 0x001c
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#define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
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#define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
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#define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
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#define CSR7_TXDONE_TXRING FIELD32(0x00000008)
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#define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
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#define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
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#define CSR7_RXDONE FIELD32(0x00000040)
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/*
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* CSR8: Interrupt mask register.
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* Write 1 to mask interrupt.
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* TBCN_EXPIRE: Beacon timer expired interrupt.
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* TWAKE_EXPIRE: Wakeup timer expired interrupt.
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* TATIMW_EXPIRE: Timer of atim window expired interrupt.
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* TXDONE_TXRING: Tx ring transmit done interrupt.
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* TXDONE_ATIMRING: Atim ring transmit done interrupt.
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* TXDONE_PRIORING: Priority ring transmit done interrupt.
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* RXDONE: Receive done interrupt.
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*/
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#define CSR8 0x0020
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#define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
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#define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
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#define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
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#define CSR8_TXDONE_TXRING FIELD32(0x00000008)
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#define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
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#define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
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#define CSR8_RXDONE FIELD32(0x00000040)
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/*
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* CSR9: Maximum frame length register.
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* MAX_FRAME_UNIT: Maximum frame length in 128b unit, default: 12.
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*/
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#define CSR9 0x0024
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#define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
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/*
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* CSR11: Back-off control register.
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* CWMIN: CWmin. Default cwmin is 31 (2^5 - 1).
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* CWMAX: CWmax. Default cwmax is 1023 (2^10 - 1).
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* SLOT_TIME: Slot time, default is 20us for 802.11b.
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* LONG_RETRY: Long retry count.
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* SHORT_RETRY: Short retry count.
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*/
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#define CSR11 0x002c
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#define CSR11_CWMIN FIELD32(0x0000000f)
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#define CSR11_CWMAX FIELD32(0x000000f0)
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#define CSR11_SLOT_TIME FIELD32(0x00001f00)
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#define CSR11_LONG_RETRY FIELD32(0x00ff0000)
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#define CSR11_SHORT_RETRY FIELD32(0xff000000)
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/*
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* CSR12: Synchronization configuration register 0.
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* All units in 1/16 TU.
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* BEACON_INTERVAL: Beacon interval, default is 100 TU.
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* CFPMAX_DURATION: Cfp maximum duration, default is 100 TU.
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*/
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#define CSR12 0x0030
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#define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
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#define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
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/*
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* CSR13: Synchronization configuration register 1.
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* All units in 1/16 TU.
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* ATIMW_DURATION: Atim window duration.
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* CFP_PERIOD: Cfp period, default is 0 TU.
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*/
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#define CSR13 0x0034
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#define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
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#define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
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/*
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* CSR14: Synchronization control register.
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* TSF_COUNT: Enable tsf auto counting.
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* TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
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* TBCN: Enable tbcn with reload value.
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* TCFP: Enable tcfp & cfp / cp switching.
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* TATIMW: Enable tatimw & atim window switching.
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* BEACON_GEN: Enable beacon generator.
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* CFP_COUNT_PRELOAD: Cfp count preload value.
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* TBCM_PRELOAD: Tbcn preload value in units of 64us.
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*/
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#define CSR14 0x0038
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#define CSR14_TSF_COUNT FIELD32(0x00000001)
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#define CSR14_TSF_SYNC FIELD32(0x00000006)
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#define CSR14_TBCN FIELD32(0x00000008)
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#define CSR14_TCFP FIELD32(0x00000010)
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#define CSR14_TATIMW FIELD32(0x00000020)
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#define CSR14_BEACON_GEN FIELD32(0x00000040)
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#define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
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#define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
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/*
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* CSR15: Synchronization status register.
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* CFP: ASIC is in contention-free period.
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* ATIMW: ASIC is in ATIM window.
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* BEACON_SENT: Beacon is send.
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*/
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#define CSR15 0x003c
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#define CSR15_CFP FIELD32(0x00000001)
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#define CSR15_ATIMW FIELD32(0x00000002)
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#define CSR15_BEACON_SENT FIELD32(0x00000004)
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/*
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* CSR16: TSF timer register 0.
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*/
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#define CSR16 0x0040
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#define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
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/*
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* CSR17: TSF timer register 1.
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*/
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#define CSR17 0x0044
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#define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
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/*
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* CSR18: IFS timer register 0.
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* SIFS: Sifs, default is 10 us.
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* PIFS: Pifs, default is 30 us.
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*/
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#define CSR18 0x0048
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#define CSR18_SIFS FIELD32(0x0000ffff)
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#define CSR18_PIFS FIELD32(0xffff0000)
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/*
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* CSR19: IFS timer register 1.
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* DIFS: Difs, default is 50 us.
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* EIFS: Eifs, default is 364 us.
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*/
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#define CSR19 0x004c
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#define CSR19_DIFS FIELD32(0x0000ffff)
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#define CSR19_EIFS FIELD32(0xffff0000)
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/*
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* CSR20: Wakeup timer register.
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* DELAY_AFTER_TBCN: Delay after tbcn expired in units of 1/16 TU.
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* TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
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* AUTOWAKE: Enable auto wakeup / sleep mechanism.
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*/
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#define CSR20 0x0050
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#define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
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#define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
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#define CSR20_AUTOWAKE FIELD32(0x01000000)
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/*
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* CSR21: EEPROM control register.
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* RELOAD: Write 1 to reload eeprom content.
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* TYPE_93C46: 1: 93c46, 0:93c66.
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*/
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#define CSR21 0x0054
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#define CSR21_RELOAD FIELD32(0x00000001)
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#define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
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#define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
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#define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
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#define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
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#define CSR21_TYPE_93C46 FIELD32(0x00000020)
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/*
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* CSR22: CFP control register.
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* CFP_DURATION_REMAIN: Cfp duration remain, in units of TU.
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* RELOAD_CFP_DURATION: Write 1 to reload cfp duration remain.
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*/
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#define CSR22 0x0058
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#define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
|
|
|
|
|
#define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Transmit related CSRs.
|
|
|
|
|
* Some values are set in TU, whereas 1 TU == 1024 us.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR0: TX Control Register.
|
|
|
|
|
* KICK_TX: Kick tx ring.
|
|
|
|
|
* KICK_ATIM: Kick atim ring.
|
|
|
|
|
* KICK_PRIO: Kick priority ring.
|
|
|
|
|
* ABORT: Abort all transmit related ring operation.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR0 0x0060
|
|
|
|
|
#define TXCSR0_KICK_TX FIELD32(0x00000001)
|
|
|
|
|
#define TXCSR0_KICK_ATIM FIELD32(0x00000002)
|
|
|
|
|
#define TXCSR0_KICK_PRIO FIELD32(0x00000004)
|
|
|
|
|
#define TXCSR0_ABORT FIELD32(0x00000008)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR1: TX Configuration Register.
|
|
|
|
|
* ACK_TIMEOUT: Ack timeout, default = sifs + 2*slottime + acktime @ 1mbps.
|
|
|
|
|
* ACK_CONSUME_TIME: Ack consume time, default = sifs + acktime @ 1mbps.
|
|
|
|
|
* TSF_OFFSET: Insert tsf offset.
|
|
|
|
|
* AUTORESPONDER: Enable auto responder which include ack & cts.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR1 0x0064
|
|
|
|
|
#define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
|
|
|
|
|
#define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
|
|
|
|
|
#define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
|
|
|
|
|
#define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR2: Tx descriptor configuration register.
|
|
|
|
|
* TXD_SIZE: Tx descriptor size, default is 48.
|
|
|
|
|
* NUM_TXD: Number of tx entries in ring.
|
|
|
|
|
* NUM_ATIM: Number of atim entries in ring.
|
|
|
|
|
* NUM_PRIO: Number of priority entries in ring.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR2 0x0068
|
|
|
|
|
#define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
|
|
|
|
|
#define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
|
|
|
|
|
#define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
|
|
|
|
|
#define TXCSR2_NUM_PRIO FIELD32(0xff000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR3: TX Ring Base address register.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR3 0x006c
|
|
|
|
|
#define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR4: TX Atim Ring Base address register.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR4 0x0070
|
|
|
|
|
#define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR5: TX Prio Ring Base address register.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR5 0x0074
|
|
|
|
|
#define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR6: Beacon Base address register.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR6 0x0078
|
|
|
|
|
#define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TXCSR7: Auto responder control register.
|
|
|
|
|
* AR_POWERMANAGEMENT: Auto responder power management bit.
|
|
|
|
|
*/
|
|
|
|
|
#define TXCSR7 0x007c
|
|
|
|
|
#define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Receive related CSRs.
|
|
|
|
|
* Some values are set in TU, whereas 1 TU == 1024 us.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RXCSR0: RX Control Register.
|
|
|
|
|
* DISABLE_RX: Disable rx engine.
|
|
|
|
|
* DROP_CRC: Drop crc error.
|
|
|
|
|
* DROP_PHYSICAL: Drop physical error.
|
|
|
|
|
* DROP_CONTROL: Drop control frame.
|
|
|
|
|
* DROP_NOT_TO_ME: Drop not to me unicast frame.
|
|
|
|
|
* DROP_TODS: Drop frame tods bit is true.
|
|
|
|
|
* DROP_VERSION_ERROR: Drop version error frame.
|
|
|
|
|
* PASS_CRC: Pass all packets with crc attached.
|
|
|
|
|
*/
|
|
|
|
|
#define RXCSR0 0x0080
|
|
|
|
|
#define RXCSR0_DISABLE_RX FIELD32(0x00000001)
|
|
|
|
|
#define RXCSR0_DROP_CRC FIELD32(0x00000002)
|
|
|
|
|
#define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
|
|
|
|
|
#define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
|
|
|
|
|
#define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
|
|
|
|
|
#define RXCSR0_DROP_TODS FIELD32(0x00000020)
|
|
|
|
|
#define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
|
|
|
|
|
#define RXCSR0_PASS_CRC FIELD32(0x00000080)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RXCSR1: RX descriptor configuration register.
|
|
|
|
|
* RXD_SIZE: Rx descriptor size, default is 32b.
|
|
|
|
|
* NUM_RXD: Number of rx entries in ring.
|
|
|
|
|
*/
|
|
|
|
|
#define RXCSR1 0x0084
|
|
|
|
|
#define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
|
|
|
|
|
#define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RXCSR2: RX Ring base address register.
|
|
|
|
|
*/
|
|
|
|
|
#define RXCSR2 0x0088
|
|
|
|
|
#define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RXCSR3: BBP ID register for Rx operation.
|
|
|
|
|
* BBP_ID#: BBP register # id.
|
|
|
|
|
* BBP_ID#_VALID: BBP register # id is valid or not.
|
|
|
|
|
*/
|
|
|
|
|
#define RXCSR3 0x0090
|
|
|
|
|
#define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
|
|
|
|
|
#define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
|
|
|
|
|
#define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
|
|
|
|
|
#define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
|
|
|
|
|
#define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
|
|
|
|
|
#define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
|
|
|
|
|
#define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
|
|
|
|
|
#define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RXCSR4: BBP ID register for Rx operation.
|
|
|
|
|
* BBP_ID#: BBP register # id.
|
|
|
|
|
* BBP_ID#_VALID: BBP register # id is valid or not.
|
|
|
|
|
*/
|
|
|
|
|
#define RXCSR4 0x0094
|
|
|
|
|
#define RXCSR4_BBP_ID4 FIELD32(0x0000007f)
|
|
|
|
|
#define RXCSR4_BBP_ID4_VALID FIELD32(0x00000080)
|
|
|
|
|
#define RXCSR4_BBP_ID5 FIELD32(0x00007f00)
|
|
|
|
|
#define RXCSR4_BBP_ID5_VALID FIELD32(0x00008000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ARCSR0: Auto Responder PLCP config register 0.
|
|
|
|
|
* ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
|
|
|
|
|
* ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCSR0 0x0098
|
|
|
|
|
#define ARCSR0_AR_BBP_DATA0 FIELD32(0x000000ff)
|
|
|
|
|
#define ARCSR0_AR_BBP_ID0 FIELD32(0x0000ff00)
|
|
|
|
|
#define ARCSR0_AR_BBP_DATA1 FIELD32(0x00ff0000)
|
|
|
|
|
#define ARCSR0_AR_BBP_ID1 FIELD32(0xff000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ARCSR1: Auto Responder PLCP config register 1.
|
|
|
|
|
* ARCSR0_AR_BBP_DATA#: Auto responder BBP register # data.
|
|
|
|
|
* ARCSR0_AR_BBP_ID#: Auto responder BBP register # Id.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCSR1 0x009c
|
|
|
|
|
#define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
|
|
|
|
|
#define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
|
|
|
|
|
#define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
|
|
|
|
|
#define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Miscellaneous Registers.
|
|
|
|
|
* Some values are set in TU, whereas 1 TU == 1024 us.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PCICSR: PCI control register.
|
|
|
|
|
* BIG_ENDIAN: 1: big endian, 0: little endian.
|
|
|
|
|
* RX_TRESHOLD: Rx threshold in dw to start pci access
|
|
|
|
|
* 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
|
|
|
|
|
* TX_TRESHOLD: Tx threshold in dw to start pci access
|
|
|
|
|
* 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
|
|
|
|
|
* BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
|
|
|
|
|
* ENABLE_CLK: Enable clk_run, pci clock can't going down to non-operational.
|
|
|
|
|
*/
|
|
|
|
|
#define PCICSR 0x008c
|
|
|
|
|
#define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
|
|
|
|
|
#define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
|
|
|
|
|
#define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
|
|
|
|
|
#define PCICSR_BURST_LENTH FIELD32(0x00000060)
|
|
|
|
|
#define PCICSR_ENABLE_CLK FIELD32(0x00000080)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CNT0: FCS error count.
|
|
|
|
|
* FCS_ERROR: FCS error count, cleared when read.
|
|
|
|
|
*/
|
|
|
|
|
#define CNT0 0x00a0
|
|
|
|
|
#define CNT0_FCS_ERROR FIELD32(0x0000ffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Statistic Register.
|
|
|
|
|
* CNT1: PLCP error count.
|
|
|
|
|
* CNT2: Long error count.
|
|
|
|
|
* CNT3: CCA false alarm count.
|
|
|
|
|
* CNT4: Rx FIFO overflow count.
|
|
|
|
|
* CNT5: Tx FIFO underrun count.
|
|
|
|
|
*/
|
|
|
|
|
#define TIMECSR2 0x00a8
|
|
|
|
|
#define CNT1 0x00ac
|
|
|
|
|
#define CNT2 0x00b0
|
|
|
|
|
#define TIMECSR3 0x00b4
|
|
|
|
|
#define CNT3 0x00b8
|
|
|
|
|
#define CNT4 0x00bc
|
|
|
|
|
#define CNT5 0x00c0
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Baseband Control Register.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PWRCSR0: Power mode configuration register.
|
|
|
|
|
*/
|
|
|
|
|
#define PWRCSR0 0x00c4
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Power state transition time registers.
|
|
|
|
|
*/
|
|
|
|
|
#define PSCSR0 0x00c8
|
|
|
|
|
#define PSCSR1 0x00cc
|
|
|
|
|
#define PSCSR2 0x00d0
|
|
|
|
|
#define PSCSR3 0x00d4
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* PWRCSR1: Manual power control / status register.
|
|
|
|
|
* Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
|
|
|
|
|
* SET_STATE: Set state. Write 1 to trigger, self cleared.
|
|
|
|
|
* BBP_DESIRE_STATE: BBP desired state.
|
|
|
|
|
* RF_DESIRE_STATE: RF desired state.
|
|
|
|
|
* BBP_CURR_STATE: BBP current state.
|
|
|
|
|
* RF_CURR_STATE: RF current state.
|
|
|
|
|
* PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
|
|
|
|
|
*/
|
|
|
|
|
#define PWRCSR1 0x00d8
|
|
|
|
|
#define PWRCSR1_SET_STATE FIELD32(0x00000001)
|
|
|
|
|
#define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
|
|
|
|
|
#define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
|
|
|
|
|
#define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
|
|
|
|
|
#define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
|
|
|
|
|
#define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TIMECSR: Timer control register.
|
|
|
|
|
* US_COUNT: 1 us timer count in units of clock cycles.
|
|
|
|
|
* US_64_COUNT: 64 us timer count in units of 1 us timer.
|
|
|
|
|
* BEACON_EXPECT: Beacon expect window.
|
|
|
|
|
*/
|
|
|
|
|
#define TIMECSR 0x00dc
|
|
|
|
|
#define TIMECSR_US_COUNT FIELD32(0x000000ff)
|
|
|
|
|
#define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
|
|
|
|
|
#define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* MACCSR0: MAC configuration register 0.
|
|
|
|
|
*/
|
|
|
|
|
#define MACCSR0 0x00e0
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* MACCSR1: MAC configuration register 1.
|
|
|
|
|
* KICK_RX: Kick one-shot rx in one-shot rx mode.
|
|
|
|
|
* ONESHOT_RXMODE: Enable one-shot rx mode for debugging.
|
|
|
|
|
* BBPRX_RESET_MODE: Ralink bbp rx reset mode.
|
|
|
|
|
* AUTO_TXBBP: Auto tx logic access bbp control register.
|
|
|
|
|
* AUTO_RXBBP: Auto rx logic access bbp control register.
|
|
|
|
|
* LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
|
|
|
|
|
* INTERSIL_IF: Intersil if calibration pin.
|
|
|
|
|
*/
|
|
|
|
|
#define MACCSR1 0x00e4
|
|
|
|
|
#define MACCSR1_KICK_RX FIELD32(0x00000001)
|
|
|
|
|
#define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
|
|
|
|
|
#define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
|
|
|
|
|
#define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
|
|
|
|
|
#define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
|
|
|
|
|
#define MACCSR1_LOOPBACK FIELD32(0x00000060)
|
|
|
|
|
#define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RALINKCSR: Ralink Rx auto-reset BBCR.
|
|
|
|
|
* AR_BBP_DATA#: Auto reset BBP register # data.
|
|
|
|
|
* AR_BBP_ID#: Auto reset BBP register # id.
|
|
|
|
|
*/
|
|
|
|
|
#define RALINKCSR 0x00e8
|
|
|
|
|
#define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
|
|
|
|
|
#define RALINKCSR_AR_BBP_ID0 FIELD32(0x0000ff00)
|
|
|
|
|
#define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
|
|
|
|
|
#define RALINKCSR_AR_BBP_ID1 FIELD32(0xff000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BCNCSR: Beacon interval control register.
|
|
|
|
|
* CHANGE: Write one to change beacon interval.
|
|
|
|
|
* DELTATIME: The delta time value.
|
|
|
|
|
* NUM_BEACON: Number of beacon according to mode.
|
|
|
|
|
* MODE: Please refer to asic specs.
|
|
|
|
|
* PLUS: Plus or minus delta time value.
|
|
|
|
|
*/
|
|
|
|
|
#define BCNCSR 0x00ec
|
|
|
|
|
#define BCNCSR_CHANGE FIELD32(0x00000001)
|
|
|
|
|
#define BCNCSR_DELTATIME FIELD32(0x0000001e)
|
|
|
|
|
#define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
|
|
|
|
|
#define BCNCSR_MODE FIELD32(0x00006000)
|
|
|
|
|
#define BCNCSR_PLUS FIELD32(0x00008000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BBP / RF / IF Control Register.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BBPCSR: BBP serial control register.
|
|
|
|
|
* VALUE: Register value to program into BBP.
|
|
|
|
|
* REGNUM: Selected BBP register.
|
|
|
|
|
* BUSY: 1: asic is busy execute BBP programming.
|
|
|
|
|
* WRITE_CONTROL: 1: write BBP, 0: read BBP.
|
|
|
|
|
*/
|
|
|
|
|
#define BBPCSR 0x00f0
|
|
|
|
|
#define BBPCSR_VALUE FIELD32(0x000000ff)
|
|
|
|
|
#define BBPCSR_REGNUM FIELD32(0x00007f00)
|
|
|
|
|
#define BBPCSR_BUSY FIELD32(0x00008000)
|
|
|
|
|
#define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RFCSR: RF serial control register.
|
|
|
|
|
* VALUE: Register value + id to program into rf/if.
|
|
|
|
|
* NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
|
|
|
|
|
* IF_SELECT: Chip to program: 0: rf, 1: if.
|
|
|
|
|
* PLL_LD: Rf pll_ld status.
|
|
|
|
|
* BUSY: 1: asic is busy execute rf programming.
|
|
|
|
|
*/
|
|
|
|
|
#define RFCSR 0x00f4
|
|
|
|
|
#define RFCSR_VALUE FIELD32(0x00ffffff)
|
|
|
|
|
#define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
|
|
|
|
|
#define RFCSR_IF_SELECT FIELD32(0x20000000)
|
|
|
|
|
#define RFCSR_PLL_LD FIELD32(0x40000000)
|
|
|
|
|
#define RFCSR_BUSY FIELD32(0x80000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* LEDCSR: LED control register.
|
|
|
|
|
* ON_PERIOD: On period, default 70ms.
|
|
|
|
|
* OFF_PERIOD: Off period, default 30ms.
|
|
|
|
|
* LINK: 0: linkoff, 1: linkup.
|
|
|
|
|
* ACTIVITY: 0: idle, 1: active.
|
|
|
|
|
*/
|
|
|
|
|
#define LEDCSR 0x00f8
|
|
|
|
|
#define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
|
|
|
|
|
#define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
|
|
|
|
|
#define LEDCSR_LINK FIELD32(0x00010000)
|
|
|
|
|
#define LEDCSR_ACTIVITY FIELD32(0x00020000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ASIC pointer information.
|
|
|
|
|
* RXPTR: Current RX ring address.
|
|
|
|
|
* TXPTR: Current Tx ring address.
|
|
|
|
|
* PRIPTR: Current Priority ring address.
|
|
|
|
|
* ATIMPTR: Current ATIM ring address.
|
|
|
|
|
*/
|
|
|
|
|
#define RXPTR 0x0100
|
|
|
|
|
#define TXPTR 0x0104
|
|
|
|
|
#define PRIPTR 0x0108
|
|
|
|
|
#define ATIMPTR 0x010c
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* GPIO and others.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* GPIOCSR: GPIO control register.
|
2012-08-31 19:22:13 +02:00
|
|
|
* GPIOCSR_VALx: Actual GPIO pin x value
|
|
|
|
|
* GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
|
2007-09-25 17:57:13 -07:00
|
|
|
*/
|
|
|
|
|
#define GPIOCSR 0x0120
|
2012-08-31 19:22:13 +02:00
|
|
|
#define GPIOCSR_VAL0 FIELD32(0x00000001)
|
|
|
|
|
#define GPIOCSR_VAL1 FIELD32(0x00000002)
|
|
|
|
|
#define GPIOCSR_VAL2 FIELD32(0x00000004)
|
|
|
|
|
#define GPIOCSR_VAL3 FIELD32(0x00000008)
|
|
|
|
|
#define GPIOCSR_VAL4 FIELD32(0x00000010)
|
|
|
|
|
#define GPIOCSR_VAL5 FIELD32(0x00000020)
|
|
|
|
|
#define GPIOCSR_VAL6 FIELD32(0x00000040)
|
|
|
|
|
#define GPIOCSR_VAL7 FIELD32(0x00000080)
|
|
|
|
|
#define GPIOCSR_DIR0 FIELD32(0x00000100)
|
|
|
|
|
#define GPIOCSR_DIR1 FIELD32(0x00000200)
|
|
|
|
|
#define GPIOCSR_DIR2 FIELD32(0x00000400)
|
|
|
|
|
#define GPIOCSR_DIR3 FIELD32(0x00000800)
|
|
|
|
|
#define GPIOCSR_DIR4 FIELD32(0x00001000)
|
|
|
|
|
#define GPIOCSR_DIR5 FIELD32(0x00002000)
|
|
|
|
|
#define GPIOCSR_DIR6 FIELD32(0x00004000)
|
|
|
|
|
#define GPIOCSR_DIR7 FIELD32(0x00008000)
|
2007-09-25 17:57:13 -07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BBPPCSR: BBP Pin control register.
|
|
|
|
|
*/
|
|
|
|
|
#define BBPPCSR 0x0124
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BCNCSR1: Tx BEACON offset time control register.
|
|
|
|
|
* PRELOAD: Beacon timer offset in units of usec.
|
|
|
|
|
*/
|
|
|
|
|
#define BCNCSR1 0x0130
|
|
|
|
|
#define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* MACCSR2: TX_PE to RX_PE turn-around time control register
|
|
|
|
|
* DELAY: RX_PE low width, in units of pci clock cycle.
|
|
|
|
|
*/
|
|
|
|
|
#define MACCSR2 0x0134
|
|
|
|
|
#define MACCSR2_DELAY FIELD32(0x000000ff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ARCSR2: 1 Mbps ACK/CTS PLCP.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCSR2 0x013c
|
|
|
|
|
#define ARCSR2_SIGNAL FIELD32(0x000000ff)
|
|
|
|
|
#define ARCSR2_SERVICE FIELD32(0x0000ff00)
|
|
|
|
|
#define ARCSR2_LENGTH_LOW FIELD32(0x00ff0000)
|
|
|
|
|
#define ARCSR2_LENGTH FIELD32(0xffff0000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ARCSR3: 2 Mbps ACK/CTS PLCP.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCSR3 0x0140
|
|
|
|
|
#define ARCSR3_SIGNAL FIELD32(0x000000ff)
|
|
|
|
|
#define ARCSR3_SERVICE FIELD32(0x0000ff00)
|
|
|
|
|
#define ARCSR3_LENGTH FIELD32(0xffff0000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ARCSR4: 5.5 Mbps ACK/CTS PLCP.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCSR4 0x0144
|
|
|
|
|
#define ARCSR4_SIGNAL FIELD32(0x000000ff)
|
|
|
|
|
#define ARCSR4_SERVICE FIELD32(0x0000ff00)
|
|
|
|
|
#define ARCSR4_LENGTH FIELD32(0xffff0000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* ARCSR5: 11 Mbps ACK/CTS PLCP.
|
|
|
|
|
*/
|
|
|
|
|
#define ARCSR5 0x0148
|
|
|
|
|
#define ARCSR5_SIGNAL FIELD32(0x000000ff)
|
|
|
|
|
#define ARCSR5_SERVICE FIELD32(0x0000ff00)
|
|
|
|
|
#define ARCSR5_LENGTH FIELD32(0xffff0000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* BBP registers.
|
|
|
|
|
* The wordsize of the BBP is 8 bits.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* R1: TX antenna control
|
|
|
|
|
*/
|
|
|
|
|
#define BBP_R1_TX_ANTENNA FIELD8(0x03)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* R4: RX antenna control
|
|
|
|
|
*/
|
|
|
|
|
#define BBP_R4_RX_ANTENNA FIELD8(0x06)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RF registers
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RF 1
|
|
|
|
|
*/
|
|
|
|
|
#define RF1_TUNER FIELD32(0x00020000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* RF 3
|
|
|
|
|
*/
|
|
|
|
|
#define RF3_TUNER FIELD32(0x00000100)
|
|
|
|
|
#define RF3_TXPOWER FIELD32(0x00003e00)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* EEPROM content.
|
|
|
|
|
* The wordsize of the EEPROM is 16 bits.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* HW MAC address.
|
|
|
|
|
*/
|
|
|
|
|
#define EEPROM_MAC_ADDR_0 0x0002
|
|
|
|
|
#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
|
|
|
|
|
#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
|
|
|
|
|
#define EEPROM_MAC_ADDR1 0x0003
|
|
|
|
|
#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
|
|
|
|
|
#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
|
|
|
|
|
#define EEPROM_MAC_ADDR_2 0x0004
|
|
|
|
|
#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
|
|
|
|
|
#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* EEPROM antenna.
|
|
|
|
|
* ANTENNA_NUM: Number of antenna's.
|
|
|
|
|
* TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
|
|
|
|
|
* RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
|
|
|
|
|
* RF_TYPE: Rf_type of this adapter.
|
|
|
|
|
* LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
|
|
|
|
|
* RX_AGCVGC: 0: disable, 1:enable BBP R13 tuning.
|
|
|
|
|
* HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
|
|
|
|
|
*/
|
|
|
|
|
#define EEPROM_ANTENNA 0x0b
|
|
|
|
|
#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
|
|
|
|
|
#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
|
|
|
|
|
#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
|
|
|
|
|
#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0040)
|
|
|
|
|
#define EEPROM_ANTENNA_LED_MODE FIELD16(0x0180)
|
|
|
|
|
#define EEPROM_ANTENNA_RX_AGCVGC_TUNING FIELD16(0x0200)
|
|
|
|
|
#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* EEPROM BBP.
|
|
|
|
|
*/
|
|
|
|
|
#define EEPROM_BBP_START 0x0c
|
|
|
|
|
#define EEPROM_BBP_SIZE 7
|
|
|
|
|
#define EEPROM_BBP_VALUE FIELD16(0x00ff)
|
|
|
|
|
#define EEPROM_BBP_REG_ID FIELD16(0xff00)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* EEPROM TXPOWER
|
|
|
|
|
*/
|
|
|
|
|
#define EEPROM_TXPOWER_START 0x13
|
|
|
|
|
#define EEPROM_TXPOWER_SIZE 7
|
|
|
|
|
#define EEPROM_TXPOWER_1 FIELD16(0x00ff)
|
|
|
|
|
#define EEPROM_TXPOWER_2 FIELD16(0xff00)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* DMA descriptor defines.
|
|
|
|
|
*/
|
2010-11-06 15:44:00 +01:00
|
|
|
#define TXD_DESC_SIZE (8 * sizeof(__le32))
|
|
|
|
|
#define RXD_DESC_SIZE (8 * sizeof(__le32))
|
2007-09-25 17:57:13 -07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Word0
|
|
|
|
|
*/
|
|
|
|
|
#define TXD_W0_OWNER_NIC FIELD32(0x00000001)
|
|
|
|
|
#define TXD_W0_VALID FIELD32(0x00000002)
|
|
|
|
|
#define TXD_W0_RESULT FIELD32(0x0000001c)
|
|
|
|
|
#define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
|
|
|
|
|
#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
|
|
|
|
|
#define TXD_W0_ACK FIELD32(0x00000200)
|
|
|
|
|
#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
|
|
|
|
|
#define TXD_W0_RTS FIELD32(0x00000800)
|
|
|
|
|
#define TXD_W0_IFS FIELD32(0x00006000)
|
|
|
|
|
#define TXD_W0_RETRY_MODE FIELD32(0x00008000)
|
|
|
|
|
#define TXD_W0_AGC FIELD32(0x00ff0000)
|
|
|
|
|
#define TXD_W0_R2 FIELD32(0xff000000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Word1
|
|
|
|
|
*/
|
|
|
|
|
#define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Word2
|
|
|
|
|
*/
|
|
|
|
|
#define TXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
|
|
|
|
|
#define TXD_W2_DATABYTE_COUNT FIELD32(0xffff0000)
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Word3 & 4: PLCP information
|
2007-11-27 21:47:56 +01:00
|
|
|
* The PLCP values should be treated as if they were BBP values.
|
|
|
|
|
*/
|
|
|
|
|
#define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
|
|
|
|
|
#define TXD_W3_PLCP_SIGNAL_REGNUM FIELD32(0x00007f00)
|
|
|
|
|
#define TXD_W3_PLCP_SIGNAL_BUSY FIELD32(0x00008000)
|
|
|
|
|
#define TXD_W3_PLCP_SERVICE FIELD32(0x00ff0000)
|
|
|
|
|
#define TXD_W3_PLCP_SERVICE_REGNUM FIELD32(0x7f000000)
|
|
|
|
|
#define TXD_W3_PLCP_SERVICE_BUSY FIELD32(0x80000000)
|
|
|
|
|
|
|
|
|
|
#define TXD_W4_PLCP_LENGTH_LOW FIELD32(0x000000ff)
|
|
|
|
|
#define TXD_W3_PLCP_LENGTH_LOW_REGNUM FIELD32(0x00007f00)
|
|
|
|
|
#define TXD_W3_PLCP_LENGTH_LOW_BUSY FIELD32(0x00008000)
|
|
|
|
|
#define TXD_W4_PLCP_LENGTH_HIGH FIELD32(0x00ff0000)
|
|
|
|
|
#define TXD_W3_PLCP_LENGTH_HIGH_REGNUM FIELD32(0x7f000000)
|
|
|
|
|
#define TXD_W3_PLCP_LENGTH_HIGH_BUSY FIELD32(0x80000000)
|
2007-09-25 17:57:13 -07:00
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/*
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* Word5
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*/
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#define TXD_W5_BBCR4 FIELD32(0x0000ffff)
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#define TXD_W5_AGC_REG FIELD32(0x007f0000)
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#define TXD_W5_AGC_REG_VALID FIELD32(0x00800000)
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#define TXD_W5_XXX_REG FIELD32(0x7f000000)
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#define TXD_W5_XXX_REG_VALID FIELD32(0x80000000)
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/*
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* Word6
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*/
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#define TXD_W6_SK_BUFF FIELD32(0xffffffff)
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/*
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* Word7
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*/
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#define TXD_W7_RESERVED FIELD32(0xffffffff)
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/*
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* RX descriptor format for RX Ring.
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*/
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/*
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* Word0
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*/
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#define RXD_W0_OWNER_NIC FIELD32(0x00000001)
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#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
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#define RXD_W0_MULTICAST FIELD32(0x00000004)
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#define RXD_W0_BROADCAST FIELD32(0x00000008)
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#define RXD_W0_MY_BSS FIELD32(0x00000010)
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#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
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#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
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#define RXD_W0_DATABYTE_COUNT FIELD32(0xffff0000)
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/*
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* Word1
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*/
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#define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
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/*
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* Word2
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*/
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#define RXD_W2_BUFFER_LENGTH FIELD32(0x0000ffff)
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2008-03-09 22:49:04 +01:00
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#define RXD_W2_BBR0 FIELD32(0x00ff0000)
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#define RXD_W2_SIGNAL FIELD32(0xff000000)
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2007-09-25 17:57:13 -07:00
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/*
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* Word3
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*/
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2008-03-09 22:49:04 +01:00
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#define RXD_W3_RSSI FIELD32(0x000000ff)
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2007-09-25 17:57:13 -07:00
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#define RXD_W3_BBR3 FIELD32(0x0000ff00)
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#define RXD_W3_BBR4 FIELD32(0x00ff0000)
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#define RXD_W3_BBR5 FIELD32(0xff000000)
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/*
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* Word4
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*/
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#define RXD_W4_RX_END_TIME FIELD32(0xffffffff)
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/*
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* Word5 & 6 & 7: Reserved
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*/
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#define RXD_W5_RESERVED FIELD32(0xffffffff)
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#define RXD_W6_RESERVED FIELD32(0xffffffff)
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#define RXD_W7_RESERVED FIELD32(0xffffffff)
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/*
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2009-07-17 21:39:19 +02:00
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* Macros for converting txpower from EEPROM to mac80211 value
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2008-02-17 17:34:26 +01:00
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* and from mac80211 value to register value.
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2007-09-25 17:57:13 -07:00
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* NOTE: Logics in rt2400pci for txpower are reversed
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* compared to the other rt2x00 drivers. A higher txpower
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* value means that the txpower must be lowered. This is
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* important when converting the value coming from the
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2008-02-17 17:34:26 +01:00
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* mac80211 stack to the rt2400 acceptable value.
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2007-09-25 17:57:13 -07:00
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*/
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#define MIN_TXPOWER 31
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#define MAX_TXPOWER 62
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#define DEFAULT_TXPOWER 39
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2008-08-04 16:38:47 +02:00
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#define __CLAMP_TX(__txpower) \
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clamp_t(char, (__txpower), MIN_TXPOWER, MAX_TXPOWER)
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#define TXPOWER_FROM_DEV(__txpower) \
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((__CLAMP_TX(__txpower) - MAX_TXPOWER) + MIN_TXPOWER)
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#define TXPOWER_TO_DEV(__txpower) \
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2010-11-06 15:44:00 +01:00
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(MAX_TXPOWER - (__CLAMP_TX(__txpower) - MIN_TXPOWER))
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2007-09-25 17:57:13 -07:00
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#endif /* RT2400PCI_H */
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