616 lines
17 KiB
C
616 lines
17 KiB
C
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/*
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* SH7269 Setup
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*
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* Copyright (C) 2012 Renesas Electronics Europe Ltd
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* Copyright (C) 2012 Phil Edworthy
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/usb/r8a66597.h>
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#include <linux/sh_timer.h>
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#include <linux/io.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
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USB, VDC4, CMT0, CMT1, BSC, WDT,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
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PWMT1, PWMT2, ADC_ADI,
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SSIF0, SSII1, SSII2, SSII3, SSII4, SSII5,
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RSPDIF,
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IIC30, IIC31, IIC32, IIC33,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
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SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
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SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
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SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
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RCAN0, RCAN1, RCAN2,
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RSPIC0, RSPIC1,
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IEBC, CD_ROMD,
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NFMC,
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SDHI0, SDHI1,
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RTC,
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SRCC0, SRCC1, SRCC2,
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/* interrupt groups */
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PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
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INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
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INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
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INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
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INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
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INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
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INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
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INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
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INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
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INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
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INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
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INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
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INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
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INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
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INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
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INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
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INTC_IRQ(USB, 170),
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INTC_IRQ(VDC4, 171), INTC_IRQ(VDC4, 172),
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INTC_IRQ(VDC4, 173), INTC_IRQ(VDC4, 174),
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INTC_IRQ(VDC4, 175), INTC_IRQ(VDC4, 176),
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INTC_IRQ(VDC4, 177), INTC_IRQ(VDC4, 177),
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INTC_IRQ(CMT0, 188), INTC_IRQ(CMT1, 189),
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INTC_IRQ(BSC, 190), INTC_IRQ(WDT, 191),
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INTC_IRQ(MTU0_ABCD, 192), INTC_IRQ(MTU0_ABCD, 193),
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INTC_IRQ(MTU0_ABCD, 194), INTC_IRQ(MTU0_ABCD, 195),
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INTC_IRQ(MTU0_VEF, 196), INTC_IRQ(MTU0_VEF, 197),
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INTC_IRQ(MTU0_VEF, 198),
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INTC_IRQ(MTU1_AB, 199), INTC_IRQ(MTU1_AB, 200),
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INTC_IRQ(MTU1_VU, 201), INTC_IRQ(MTU1_VU, 202),
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INTC_IRQ(MTU2_AB, 203), INTC_IRQ(MTU2_AB, 204),
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INTC_IRQ(MTU2_VU, 205), INTC_IRQ(MTU2_VU, 206),
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INTC_IRQ(MTU3_ABCD, 207), INTC_IRQ(MTU3_ABCD, 208),
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INTC_IRQ(MTU3_ABCD, 209), INTC_IRQ(MTU3_ABCD, 210),
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INTC_IRQ(MTU3_TCI3V, 211),
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INTC_IRQ(MTU4_ABCD, 212), INTC_IRQ(MTU4_ABCD, 213),
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INTC_IRQ(MTU4_ABCD, 214), INTC_IRQ(MTU4_ABCD, 215),
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INTC_IRQ(MTU4_TCI4V, 216),
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INTC_IRQ(PWMT1, 217), INTC_IRQ(PWMT2, 218),
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INTC_IRQ(ADC_ADI, 223),
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INTC_IRQ(SSIF0, 224), INTC_IRQ(SSIF0, 225),
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INTC_IRQ(SSIF0, 226),
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INTC_IRQ(SSII1, 227), INTC_IRQ(SSII1, 228),
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INTC_IRQ(SSII2, 229), INTC_IRQ(SSII2, 230),
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INTC_IRQ(SSII3, 231), INTC_IRQ(SSII3, 232),
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INTC_IRQ(SSII4, 233), INTC_IRQ(SSII4, 234),
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INTC_IRQ(SSII5, 235), INTC_IRQ(SSII5, 236),
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INTC_IRQ(RSPDIF, 237),
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INTC_IRQ(IIC30, 238), INTC_IRQ(IIC30, 239),
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INTC_IRQ(IIC30, 240), INTC_IRQ(IIC30, 241),
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INTC_IRQ(IIC30, 242),
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INTC_IRQ(IIC31, 243), INTC_IRQ(IIC31, 244),
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INTC_IRQ(IIC31, 245), INTC_IRQ(IIC31, 246),
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INTC_IRQ(IIC31, 247),
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INTC_IRQ(IIC32, 248), INTC_IRQ(IIC32, 249),
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INTC_IRQ(IIC32, 250), INTC_IRQ(IIC32, 251),
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INTC_IRQ(IIC32, 252),
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INTC_IRQ(IIC33, 253), INTC_IRQ(IIC33, 254),
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INTC_IRQ(IIC33, 255), INTC_IRQ(IIC33, 256),
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INTC_IRQ(IIC33, 257),
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INTC_IRQ(SCIF0_BRI, 258), INTC_IRQ(SCIF0_ERI, 259),
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INTC_IRQ(SCIF0_RXI, 260), INTC_IRQ(SCIF0_TXI, 261),
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INTC_IRQ(SCIF1_BRI, 262), INTC_IRQ(SCIF1_ERI, 263),
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INTC_IRQ(SCIF1_RXI, 264), INTC_IRQ(SCIF1_TXI, 265),
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INTC_IRQ(SCIF2_BRI, 266), INTC_IRQ(SCIF2_ERI, 267),
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INTC_IRQ(SCIF2_RXI, 268), INTC_IRQ(SCIF2_TXI, 269),
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INTC_IRQ(SCIF3_BRI, 270), INTC_IRQ(SCIF3_ERI, 271),
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INTC_IRQ(SCIF3_RXI, 272), INTC_IRQ(SCIF3_TXI, 273),
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INTC_IRQ(SCIF4_BRI, 274), INTC_IRQ(SCIF4_ERI, 275),
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INTC_IRQ(SCIF4_RXI, 276), INTC_IRQ(SCIF4_TXI, 277),
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INTC_IRQ(SCIF5_BRI, 278), INTC_IRQ(SCIF5_ERI, 279),
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INTC_IRQ(SCIF5_RXI, 280), INTC_IRQ(SCIF5_TXI, 281),
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INTC_IRQ(SCIF6_BRI, 282), INTC_IRQ(SCIF6_ERI, 283),
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INTC_IRQ(SCIF6_RXI, 284), INTC_IRQ(SCIF6_TXI, 285),
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INTC_IRQ(SCIF7_BRI, 286), INTC_IRQ(SCIF7_ERI, 287),
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INTC_IRQ(SCIF7_RXI, 288), INTC_IRQ(SCIF7_TXI, 289),
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INTC_IRQ(RCAN0, 291), INTC_IRQ(RCAN0, 292),
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INTC_IRQ(RCAN0, 293), INTC_IRQ(RCAN0, 294),
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INTC_IRQ(RCAN0, 295),
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INTC_IRQ(RCAN1, 296), INTC_IRQ(RCAN1, 297),
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INTC_IRQ(RCAN1, 298), INTC_IRQ(RCAN1, 299),
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INTC_IRQ(RCAN1, 300),
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INTC_IRQ(RCAN2, 301), INTC_IRQ(RCAN2, 302),
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INTC_IRQ(RCAN2, 303), INTC_IRQ(RCAN2, 304),
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INTC_IRQ(RCAN2, 305),
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INTC_IRQ(RSPIC0, 306), INTC_IRQ(RSPIC0, 307),
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INTC_IRQ(RSPIC0, 308),
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INTC_IRQ(RSPIC1, 309), INTC_IRQ(RSPIC1, 310),
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INTC_IRQ(RSPIC1, 311),
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INTC_IRQ(IEBC, 318),
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INTC_IRQ(CD_ROMD, 319), INTC_IRQ(CD_ROMD, 320),
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INTC_IRQ(CD_ROMD, 321), INTC_IRQ(CD_ROMD, 322),
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INTC_IRQ(CD_ROMD, 323), INTC_IRQ(CD_ROMD, 324),
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INTC_IRQ(NFMC, 325), INTC_IRQ(NFMC, 326),
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INTC_IRQ(NFMC, 327), INTC_IRQ(NFMC, 328),
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INTC_IRQ(SDHI0, 332), INTC_IRQ(SDHI0, 333),
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INTC_IRQ(SDHI0, 334),
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INTC_IRQ(SDHI1, 335), INTC_IRQ(SDHI1, 336),
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INTC_IRQ(SDHI1, 337),
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INTC_IRQ(RTC, 338), INTC_IRQ(RTC, 339),
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INTC_IRQ(RTC, 340),
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INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
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INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
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INTC_IRQ(SRCC0, 345),
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INTC_IRQ(SRCC1, 346), INTC_IRQ(SRCC1, 347),
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INTC_IRQ(SRCC1, 348), INTC_IRQ(SRCC1, 349),
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INTC_IRQ(SRCC1, 350),
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INTC_IRQ(SRCC2, 351), INTC_IRQ(SRCC2, 352),
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INTC_IRQ(SRCC2, 353), INTC_IRQ(SRCC2, 354),
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INTC_IRQ(SRCC2, 355),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
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INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
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INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
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INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
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INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
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INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
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{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
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{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8, DMAC9,
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DMAC10, DMAC11 } },
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{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
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DMAC14, DMAC15 } },
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{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC4, VDC4, VDC4 } },
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{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { 0, 0, 0, 0 } },
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{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { CMT0, CMT1, BSC, WDT } },
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{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU0_ABCD, MTU0_VEF,
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MTU1_AB, MTU1_VU } },
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{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU3_TCI3V } },
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{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { MTU4_ABCD, MTU4_TCI4V,
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PWMT1, PWMT2 } },
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{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { 0, 0, 0, 0 } },
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{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { ADC_ADI, SSIF0, SSII1, SSII2 } },
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{ 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SSII3, SSII4, SSII5, RSPDIF} },
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{ 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { IIC30, IIC31, IIC32, IIC33 } },
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{ 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
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{ 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
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{ 0xfffe0c20, 0, 16, 4, /* IPR22 */ { 0, RCAN0, RCAN1, RCAN2 } },
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{ 0xfffe0c22, 0, 16, 4, /* IPR23 */ { RSPIC0, RSPIC1, 0, 0 } },
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{ 0xfffe0c24, 0, 16, 4, /* IPR24 */ { IEBC, CD_ROMD, NFMC, 0 } },
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{ 0xfffe0c26, 0, 16, 4, /* IPR25 */ { SDHI0, SDHI1, RTC, 0 } },
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{ 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffe0808, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups,
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mask_registers, prio_registers, NULL);
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xe8007000,
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.flags = UPF_BOOT_AUTOCONF,
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.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
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||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 259, 260, 261, 258 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif0_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 0,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif0_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_sci_port scif1_platform_data = {
|
||
|
|
.mapbase = 0xe8007800,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF,
|
||
|
|
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 263, 264, 265, 262 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif1_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 1,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif1_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_sci_port scif2_platform_data = {
|
||
|
|
.mapbase = 0xe8008000,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF,
|
||
|
|
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 267, 268, 269, 266 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif2_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 2,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif2_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_sci_port scif3_platform_data = {
|
||
|
|
.mapbase = 0xe8008800,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF,
|
||
|
|
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 271, 272, 273, 270 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif3_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 3,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif3_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_sci_port scif4_platform_data = {
|
||
|
|
.mapbase = 0xe8009000,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF,
|
||
|
|
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 275, 276, 277, 274 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif4_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 4,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif4_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_sci_port scif5_platform_data = {
|
||
|
|
.mapbase = 0xe8009800,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF,
|
||
|
|
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 279, 280, 281, 278 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif5_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 5,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif5_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_sci_port scif6_platform_data = {
|
||
|
|
.mapbase = 0xe800a000,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF,
|
||
|
|
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 283, 284, 285, 282 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif6_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 6,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif6_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct plat_sci_port scif7_platform_data = {
|
||
|
|
.mapbase = 0xe800a800,
|
||
|
|
.flags = UPF_BOOT_AUTOCONF,
|
||
|
|
.scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
|
||
|
|
SCSCR_REIE | SCSCR_TOIE,
|
||
|
|
.scbrr_algo_id = SCBRR_ALGO_2,
|
||
|
|
.type = PORT_SCIF,
|
||
|
|
.irqs = { 287, 288, 289, 286 },
|
||
|
|
.regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device scif7_device = {
|
||
|
|
.name = "sh-sci",
|
||
|
|
.id = 7,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &scif7_platform_data,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct sh_timer_config cmt0_platform_data = {
|
||
|
|
.channel_offset = 0x02,
|
||
|
|
.timer_bit = 0,
|
||
|
|
.clockevent_rating = 125,
|
||
|
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource cmt0_resources[] = {
|
||
|
|
[0] = {
|
||
|
|
.start = 0xfffec002,
|
||
|
|
.end = 0xfffec007,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
[1] = {
|
||
|
|
.start = 188,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device cmt0_device = {
|
||
|
|
.name = "sh_cmt",
|
||
|
|
.id = 0,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &cmt0_platform_data,
|
||
|
|
},
|
||
|
|
.resource = cmt0_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(cmt0_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct sh_timer_config cmt1_platform_data = {
|
||
|
|
.channel_offset = 0x08,
|
||
|
|
.timer_bit = 1,
|
||
|
|
.clockevent_rating = 125,
|
||
|
|
.clocksource_rating = 0, /* disabled due to code generation issues */
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource cmt1_resources[] = {
|
||
|
|
[0] = {
|
||
|
|
.start = 0xfffec008,
|
||
|
|
.end = 0xfffec00d,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
[1] = {
|
||
|
|
.start = 189,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device cmt1_device = {
|
||
|
|
.name = "sh_cmt",
|
||
|
|
.id = 1,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &cmt1_platform_data,
|
||
|
|
},
|
||
|
|
.resource = cmt1_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(cmt1_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct sh_timer_config mtu2_0_platform_data = {
|
||
|
|
.channel_offset = -0x80,
|
||
|
|
.timer_bit = 0,
|
||
|
|
.clockevent_rating = 200,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource mtu2_0_resources[] = {
|
||
|
|
[0] = {
|
||
|
|
.start = 0xfffe4300,
|
||
|
|
.end = 0xfffe4326,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
[1] = {
|
||
|
|
.start = 192,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device mtu2_0_device = {
|
||
|
|
.name = "sh_mtu2",
|
||
|
|
.id = 0,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &mtu2_0_platform_data,
|
||
|
|
},
|
||
|
|
.resource = mtu2_0_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(mtu2_0_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct sh_timer_config mtu2_1_platform_data = {
|
||
|
|
.channel_offset = -0x100,
|
||
|
|
.timer_bit = 1,
|
||
|
|
.clockevent_rating = 200,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource mtu2_1_resources[] = {
|
||
|
|
[0] = {
|
||
|
|
.start = 0xfffe4380,
|
||
|
|
.end = 0xfffe4390,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
[1] = {
|
||
|
|
.start = 203,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device mtu2_1_device = {
|
||
|
|
.name = "sh_mtu2",
|
||
|
|
.id = 1,
|
||
|
|
.dev = {
|
||
|
|
.platform_data = &mtu2_1_platform_data,
|
||
|
|
},
|
||
|
|
.resource = mtu2_1_resources,
|
||
|
|
.num_resources = ARRAY_SIZE(mtu2_1_resources),
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource rtc_resources[] = {
|
||
|
|
[0] = {
|
||
|
|
.start = 0xfffe6000,
|
||
|
|
.end = 0xfffe6000 + 0x30 - 1,
|
||
|
|
.flags = IORESOURCE_IO,
|
||
|
|
},
|
||
|
|
[1] = {
|
||
|
|
/* Shared Period/Carry/Alarm IRQ */
|
||
|
|
.start = 338,
|
||
|
|
.flags = IORESOURCE_IRQ,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device rtc_device = {
|
||
|
|
.name = "sh-rtc",
|
||
|
|
.id = -1,
|
||
|
|
.num_resources = ARRAY_SIZE(rtc_resources),
|
||
|
|
.resource = rtc_resources,
|
||
|
|
};
|
||
|
|
|
||
|
|
/* USB Host */
|
||
|
|
static struct r8a66597_platdata r8a66597_data = {
|
||
|
|
.on_chip = 1,
|
||
|
|
.endian = 1,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct resource r8a66597_usb_host_resources[] = {
|
||
|
|
[0] = {
|
||
|
|
.start = 0xe8010000,
|
||
|
|
.end = 0xe80100e4,
|
||
|
|
.flags = IORESOURCE_MEM,
|
||
|
|
},
|
||
|
|
[1] = {
|
||
|
|
.start = 170,
|
||
|
|
.end = 170,
|
||
|
|
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device r8a66597_usb_host_device = {
|
||
|
|
.name = "r8a66597_hcd",
|
||
|
|
.id = 0,
|
||
|
|
.dev = {
|
||
|
|
.dma_mask = NULL, /* not use dma */
|
||
|
|
.coherent_dma_mask = 0xffffffff,
|
||
|
|
.platform_data = &r8a66597_data,
|
||
|
|
},
|
||
|
|
.num_resources = ARRAY_SIZE(r8a66597_usb_host_resources),
|
||
|
|
.resource = r8a66597_usb_host_resources,
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_device *sh7269_devices[] __initdata = {
|
||
|
|
&scif0_device,
|
||
|
|
&scif1_device,
|
||
|
|
&scif2_device,
|
||
|
|
&scif3_device,
|
||
|
|
&scif4_device,
|
||
|
|
&scif5_device,
|
||
|
|
&scif6_device,
|
||
|
|
&scif7_device,
|
||
|
|
&cmt0_device,
|
||
|
|
&cmt1_device,
|
||
|
|
&mtu2_0_device,
|
||
|
|
&mtu2_1_device,
|
||
|
|
&rtc_device,
|
||
|
|
&r8a66597_usb_host_device,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int __init sh7269_devices_setup(void)
|
||
|
|
{
|
||
|
|
return platform_add_devices(sh7269_devices,
|
||
|
|
ARRAY_SIZE(sh7269_devices));
|
||
|
|
}
|
||
|
|
arch_initcall(sh7269_devices_setup);
|
||
|
|
|
||
|
|
void __init plat_irq_setup(void)
|
||
|
|
{
|
||
|
|
register_intc_controller(&intc_desc);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_device *sh7269_early_devices[] __initdata = {
|
||
|
|
&scif0_device,
|
||
|
|
&scif1_device,
|
||
|
|
&scif2_device,
|
||
|
|
&scif3_device,
|
||
|
|
&scif4_device,
|
||
|
|
&scif5_device,
|
||
|
|
&scif6_device,
|
||
|
|
&scif7_device,
|
||
|
|
&cmt0_device,
|
||
|
|
&cmt1_device,
|
||
|
|
&mtu2_0_device,
|
||
|
|
&mtu2_1_device,
|
||
|
|
};
|
||
|
|
|
||
|
|
void __init plat_early_device_setup(void)
|
||
|
|
{
|
||
|
|
early_platform_add_devices(sh7269_early_devices,
|
||
|
|
ARRAY_SIZE(sh7269_early_devices));
|
||
|
|
}
|