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										 |  |  | #ifdef __KERNEL__
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							|  |  |  | #ifndef _ASM_M32R_IRQ_H
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							|  |  |  | #define _ASM_M32R_IRQ_H
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										 |  |  | #if defined(CONFIG_PLAT_USRV)
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										 |  |  | /*
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							|  |  |  |  * IRQ definitions for M32700UT | 
					
						
							|  |  |  |  *  M32700 Chip: 64 interrupts | 
					
						
							|  |  |  |  *  ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define	M32700UT_NUM_CPU_IRQ	(64)
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							|  |  |  | #define M32700UT_NUM_PLD_IRQ	(32)
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							|  |  |  | #define M32700UT_IRQ_BASE	0
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							|  |  |  | #define M32700UT_CPU_IRQ_BASE	M32700UT_IRQ_BASE
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							|  |  |  | #define M32700UT_PLD_IRQ_BASE	(M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ)
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							|  |  |  | #define NR_IRQS	(M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ)
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							|  |  |  | #elif defined(CONFIG_PLAT_M32700UT)
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							|  |  |  | /*
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							|  |  |  |  * IRQ definitions for M32700UT(Rev.C) + M32R-LAN | 
					
						
							|  |  |  |  *  M32700 Chip: 64 interrupts | 
					
						
							|  |  |  |  *  ICU of M32700UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin | 
					
						
							|  |  |  |  *  ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin | 
					
						
							|  |  |  |  *  ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define M32700UT_NUM_CPU_IRQ		(64)
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							|  |  |  | #define M32700UT_NUM_PLD_IRQ		(32)
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							|  |  |  | #define M32700UT_NUM_LCD_PLD_IRQ	(32)
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							|  |  |  | #define M32700UT_NUM_LAN_PLD_IRQ	(32)
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							|  |  |  | #define M32700UT_IRQ_BASE		0
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							|  |  |  | #define M32700UT_CPU_IRQ_BASE		(M32700UT_IRQ_BASE)
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							|  |  |  | #define M32700UT_PLD_IRQ_BASE \
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							|  |  |  | 	(M32700UT_CPU_IRQ_BASE + M32700UT_NUM_CPU_IRQ) | 
					
						
							|  |  |  | #define M32700UT_LCD_PLD_IRQ_BASE \
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							|  |  |  | 	(M32700UT_PLD_IRQ_BASE + M32700UT_NUM_PLD_IRQ) | 
					
						
							|  |  |  | #define M32700UT_LAN_PLD_IRQ_BASE \
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							|  |  |  | 	(M32700UT_LCD_PLD_IRQ_BASE + M32700UT_NUM_LCD_PLD_IRQ) | 
					
						
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							|  |  |  | #define NR_IRQS \
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							|  |  |  | 	(M32700UT_NUM_CPU_IRQ + M32700UT_NUM_PLD_IRQ \ | 
					
						
							|  |  |  | 	+ M32700UT_NUM_LCD_PLD_IRQ + M32700UT_NUM_LAN_PLD_IRQ) | 
					
						
							|  |  |  | #elif defined(CONFIG_PLAT_OPSPUT)
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							|  |  |  | /*
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							|  |  |  |  * IRQ definitions for OPSPUT + M32R-LAN | 
					
						
							|  |  |  |  *  OPSP Chip: 64 interrupts | 
					
						
							|  |  |  |  *  ICU of OPSPUT-on-board PLD: 32 interrupts cascaded to INT1# chip pin | 
					
						
							|  |  |  |  *  ICU of M32R-LCD-on-board PLD: 32 interrupts cascaded to INT2# chip pin | 
					
						
							|  |  |  |  *  ICU of M32R-LAN-on-board PLD: 32 interrupts cascaded to INT0# chip pin | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define OPSPUT_NUM_CPU_IRQ		(64)
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							|  |  |  | #define OPSPUT_NUM_PLD_IRQ		(32)
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							|  |  |  | #define OPSPUT_NUM_LCD_PLD_IRQ	(32)
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							|  |  |  | #define OPSPUT_NUM_LAN_PLD_IRQ	(32)
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							|  |  |  | #define OPSPUT_IRQ_BASE		0
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							|  |  |  | #define OPSPUT_CPU_IRQ_BASE		(OPSPUT_IRQ_BASE)
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							|  |  |  | #define OPSPUT_PLD_IRQ_BASE \
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							|  |  |  | 	(OPSPUT_CPU_IRQ_BASE + OPSPUT_NUM_CPU_IRQ) | 
					
						
							|  |  |  | #define OPSPUT_LCD_PLD_IRQ_BASE \
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							|  |  |  | 	(OPSPUT_PLD_IRQ_BASE + OPSPUT_NUM_PLD_IRQ) | 
					
						
							|  |  |  | #define OPSPUT_LAN_PLD_IRQ_BASE \
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							|  |  |  | 	(OPSPUT_LCD_PLD_IRQ_BASE + OPSPUT_NUM_LCD_PLD_IRQ) | 
					
						
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							|  |  |  | #define NR_IRQS \
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							|  |  |  | 	(OPSPUT_NUM_CPU_IRQ + OPSPUT_NUM_PLD_IRQ \ | 
					
						
							|  |  |  | 	+ OPSPUT_NUM_LCD_PLD_IRQ + OPSPUT_NUM_LAN_PLD_IRQ) | 
					
						
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							|  |  |  | #elif defined(CONFIG_PLAT_M32104UT)
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							|  |  |  | /*
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							|  |  |  |  * IRQ definitions for M32104UT | 
					
						
							|  |  |  |  *  M32104 Chip: 64 interrupts | 
					
						
							|  |  |  |  *  ICU of M32104UT-on-board PLD: 32 interrupts cascaded to INT1# chip pin | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #define	M32104UT_NUM_CPU_IRQ	(64)
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							|  |  |  | #define M32104UT_NUM_PLD_IRQ	(32)
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							|  |  |  | #define M32104UT_IRQ_BASE	0
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							|  |  |  | #define M32104UT_CPU_IRQ_BASE	M32104UT_IRQ_BASE
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							|  |  |  | #define M32104UT_PLD_IRQ_BASE	(M32104UT_CPU_IRQ_BASE + M32104UT_NUM_CPU_IRQ)
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							|  |  |  | #define NR_IRQS	\
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							|  |  |  |     (M32104UT_NUM_CPU_IRQ + M32104UT_NUM_PLD_IRQ) | 
					
						
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										 |  |  | #else
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							|  |  |  | #define NR_IRQS	64
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							|  |  |  | #endif
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							|  |  |  | #define irq_canonicalize(irq)	(irq)
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							|  |  |  | #endif /* _ASM_M32R_IRQ_H */
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							|  |  |  | #endif /* __KERNEL__ */
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