2012-07-11 15:58:56 +10:00
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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2013-10-11 15:34:08 +10:00
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#include "nv04.h"
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2009-12-11 19:24:15 +10:00
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2015-01-14 15:08:21 +10:00
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const struct nvkm_mc_intr
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2012-07-11 15:58:56 +10:00
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nv04_mc_intr[] = {
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{ 0x00000001, NVDEV_ENGINE_MPEG }, /* NV17- MPEG/ME */
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{ 0x00000100, NVDEV_ENGINE_FIFO },
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{ 0x00001000, NVDEV_ENGINE_GR },
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2013-09-07 20:33:43 -04:00
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{ 0x00010000, NVDEV_ENGINE_DISP },
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2012-07-11 15:58:56 +10:00
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{ 0x00020000, NVDEV_ENGINE_VP }, /* NV40- */
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{ 0x00100000, NVDEV_SUBDEV_TIMER },
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{ 0x01000000, NVDEV_ENGINE_DISP }, /* NV04- PCRTC0 */
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{ 0x02000000, NVDEV_ENGINE_DISP }, /* NV11- PCRTC1 */
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2012-11-04 01:01:53 +01:00
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{ 0x10000000, NVDEV_SUBDEV_BUS },
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2012-07-11 15:58:56 +10:00
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{ 0x80000000, NVDEV_ENGINE_SW },
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{}
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};
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2013-10-11 15:34:08 +10:00
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int
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2015-01-14 15:08:21 +10:00
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nv04_mc_init(struct nvkm_object *object)
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2013-10-11 15:34:08 +10:00
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{
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2015-08-20 14:54:07 +10:00
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struct nvkm_mc *mc = (void *)object;
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2015-08-20 14:54:09 +10:00
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struct nvkm_device *device = mc->subdev.device;
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2013-10-11 15:34:08 +10:00
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2015-08-20 14:54:09 +10:00
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nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */
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nvkm_wr32(device, 0x001850, 0x00000001); /* disable rom access */
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2013-10-11 15:34:08 +10:00
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2015-08-20 14:54:07 +10:00
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return nvkm_mc_init(mc);
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2013-10-11 15:34:08 +10:00
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}
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int
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2015-01-14 15:08:21 +10:00
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nv04_mc_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
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struct nvkm_oclass *oclass, void *data, u32 size,
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struct nvkm_object **pobject)
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2012-07-11 15:58:56 +10:00
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{
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2015-08-20 14:54:07 +10:00
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struct nvkm_mc *mc;
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2012-07-11 15:58:56 +10:00
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int ret;
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2010-07-10 18:10:59 +02:00
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2015-08-20 14:54:07 +10:00
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ret = nvkm_mc_create(parent, engine, oclass, &mc);
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*pobject = nv_object(mc);
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2012-07-11 15:58:56 +10:00
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if (ret)
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return ret;
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2010-07-10 18:10:59 +02:00
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2009-12-11 19:24:15 +10:00
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return 0;
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}
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2015-01-14 15:08:21 +10:00
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struct nvkm_oclass *
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nv04_mc_oclass = &(struct nvkm_mc_oclass) {
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2013-10-11 15:34:08 +10:00
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.base.handle = NV_SUBDEV(MC, 0x04),
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2015-01-14 15:08:21 +10:00
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.base.ofuncs = &(struct nvkm_ofuncs) {
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2012-07-11 15:58:56 +10:00
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.ctor = nv04_mc_ctor,
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2015-01-14 15:08:21 +10:00
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.dtor = _nvkm_mc_dtor,
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2012-07-11 15:58:56 +10:00
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.init = nv04_mc_init,
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2015-01-14 15:08:21 +10:00
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.fini = _nvkm_mc_fini,
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2012-07-11 15:58:56 +10:00
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},
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2013-10-11 15:34:08 +10:00
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.intr = nv04_mc_intr,
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}.base;
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