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										 |  |  | /*
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							|  |  |  |  * arch/sh/kernel/cpu/sh2a/clock-sh7206.c | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * SH7206 support for the clock framework | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  *  Copyright (C) 2006  Yoshinori Sato | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Based on clock-sh4.c | 
					
						
							|  |  |  |  *  Copyright (C) 2005  Paul Mundt | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * This file is subject to the terms and conditions of the GNU General Public | 
					
						
							|  |  |  |  * License.  See the file "COPYING" in the main directory of this archive | 
					
						
							|  |  |  |  * for more details. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #include <linux/init.h>
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							|  |  |  | #include <linux/kernel.h>
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							|  |  |  | #include <asm/clock.h>
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							|  |  |  | #include <asm/freq.h>
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							|  |  |  | #include <asm/io.h>
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										 |  |  | static const int pll1rate[]={1,2,3,4,6,8}; | 
					
						
							|  |  |  | static const int pfc_divisors[]={1,2,3,4,6,8,12}; | 
					
						
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										 |  |  | #define ifc_divisors pfc_divisors
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										 |  |  | static unsigned int pll2_mult; | 
					
						
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							|  |  |  | static void master_clk_init(struct clk *clk) | 
					
						
							|  |  |  | { | 
					
						
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										 |  |  | 	clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | static struct sh_clk_ops sh7206_master_clk_ops = { | 
					
						
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										 |  |  | 	.init		= master_clk_init, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | static unsigned long module_clk_recalc(struct clk *clk) | 
					
						
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										 |  |  | { | 
					
						
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										 |  |  | 	int idx = (__raw_readw(FREQCR) & 0x0007); | 
					
						
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										 |  |  | 	return clk->parent->rate / pfc_divisors[idx]; | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | static struct sh_clk_ops sh7206_module_clk_ops = { | 
					
						
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										 |  |  | 	.recalc		= module_clk_recalc, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | static unsigned long bus_clk_recalc(struct clk *clk) | 
					
						
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										 |  |  | { | 
					
						
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										 |  |  | 	return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | static struct sh_clk_ops sh7206_bus_clk_ops = { | 
					
						
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										 |  |  | 	.recalc		= bus_clk_recalc, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | static unsigned long cpu_clk_recalc(struct clk *clk) | 
					
						
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										 |  |  | { | 
					
						
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										 |  |  | 	int idx = (__raw_readw(FREQCR) & 0x0007); | 
					
						
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										 |  |  | 	return clk->parent->rate / ifc_divisors[idx]; | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | static struct sh_clk_ops sh7206_cpu_clk_ops = { | 
					
						
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										 |  |  | 	.recalc		= cpu_clk_recalc, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | static struct sh_clk_ops *sh7206_clk_ops[] = { | 
					
						
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										 |  |  | 	&sh7206_master_clk_ops, | 
					
						
							|  |  |  | 	&sh7206_module_clk_ops, | 
					
						
							|  |  |  | 	&sh7206_bus_clk_ops, | 
					
						
							|  |  |  | 	&sh7206_cpu_clk_ops, | 
					
						
							|  |  |  | }; | 
					
						
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										 |  |  | void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) | 
					
						
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										 |  |  | { | 
					
						
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										 |  |  | 	if (test_mode_pin(MODE_PIN2 | MODE_PIN1 | MODE_PIN0)) | 
					
						
							|  |  |  | 		pll2_mult = 1; | 
					
						
							|  |  |  | 	else if (test_mode_pin(MODE_PIN2 | MODE_PIN1)) | 
					
						
							|  |  |  | 		pll2_mult = 2; | 
					
						
							|  |  |  | 	else if (test_mode_pin(MODE_PIN1)) | 
					
						
							|  |  |  | 		pll2_mult = 4; | 
					
						
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										 |  |  | 	if (idx < ARRAY_SIZE(sh7206_clk_ops)) | 
					
						
							|  |  |  | 		*ops = sh7206_clk_ops[idx]; | 
					
						
							|  |  |  | } |