2012-05-10 19:46:00 +05:30
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/*
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* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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2013-05-31 14:32:56 +02:00
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#include <dt-bindings/gpio/gpio.h>
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2013-05-31 14:32:57 +02:00
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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2013-05-31 14:32:59 +02:00
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#include <dt-bindings/pinctrl/omap.h>
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2012-05-10 19:46:00 +05:30
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2013-05-31 14:32:55 +02:00
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#include "skeleton.dtsi"
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2012-05-10 19:46:00 +05:30
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/ {
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2013-02-12 15:57:55 +05:30
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#address-cells = <1>;
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#size-cells = <1>;
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2012-05-10 19:46:00 +05:30
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compatible = "ti,omap5";
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interrupt-parent = <&gic>;
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aliases {
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2013-10-16 15:21:03 -05:00
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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2012-05-10 19:46:00 +05:30
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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};
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cpus {
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2013-04-18 18:35:59 +01:00
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#address-cells = <1>;
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#size-cells = <0>;
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2013-10-16 10:39:04 -05:00
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cpu0: cpu@0 {
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2013-04-18 18:35:59 +01:00
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device_type = "cpu";
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2012-05-10 19:46:00 +05:30
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compatible = "arm,cortex-a15";
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2013-04-18 18:35:59 +01:00
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reg = <0x0>;
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2013-10-16 10:39:06 -05:00
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operating-points = <
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/* kHz uV */
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500000 880000
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1000000 1060000
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1500000 1250000
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>;
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2012-05-10 19:46:00 +05:30
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};
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cpu@1 {
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2013-04-18 18:35:59 +01:00
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device_type = "cpu";
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2012-05-10 19:46:00 +05:30
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compatible = "arm,cortex-a15";
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2013-04-18 18:35:59 +01:00
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reg = <0x1>;
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2012-05-10 19:46:00 +05:30
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};
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};
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2013-02-10 21:40:19 +05:30
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timer {
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compatible = "arm,armv7-timer";
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2013-05-31 14:32:57 +02:00
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/* PPI secure/nonsecure IRQ */
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
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2013-02-10 21:40:19 +05:30
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};
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2013-02-12 15:57:55 +05:30
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gic: interrupt-controller@48211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x48211000 0x1000>,
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2013-02-19 17:29:24 +05:30
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<0x48212000 0x1000>,
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<0x48214000 0x2000>,
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<0x48216000 0x2000>;
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2013-02-12 15:57:55 +05:30
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};
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2012-05-10 19:46:00 +05:30
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/*
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* The soc node represents the soc top level view. It is uses for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the OMAP3 interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since that will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,omap4-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
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2013-02-26 17:36:14 +05:30
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reg = <0x44000000 0x2000>,
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<0x44800000 0x3000>,
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<0x45000000 0x4000>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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2012-11-01 09:12:23 -05:00
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counter32k: counter@4ae04000 {
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compatible = "ti,omap-counter32k";
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reg = <0x4ae04000 0x40>;
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ti,hwmods = "counter_32k";
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};
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2012-10-04 14:57:27 +03:00
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omap5_pmx_core: pinmux@4a002840 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4a002840 0x01b6>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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omap5_pmx_wkup: pinmux@4ae0c840 {
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compatible = "ti,omap4-padconf", "pinctrl-single";
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reg = <0x4ae0c840 0x0038>;
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-single,register-width = <16>;
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pinctrl-single,function-mask = <0x7fff>;
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};
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2012-04-26 13:47:59 -05:00
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sdma: dma-controller@4a056000 {
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compatible = "ti,omap4430-sdma";
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reg = <0x4a056000 0x1000>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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2012-04-26 13:47:59 -05:00
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#dma-cells = <1>;
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#dma-channels = <32>;
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#dma-requests = <127>;
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};
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2012-05-10 19:46:00 +05:30
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gpio1: gpio@4ae10000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x4ae10000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio1";
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2013-04-04 15:16:16 -05:00
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ti,gpio-always-on;
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2012-05-10 19:46:00 +05:30
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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gpio2: gpio@48055000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x48055000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio2";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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gpio3: gpio@48057000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x48057000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio3";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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gpio4: gpio@48059000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x48059000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio4";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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gpio5: gpio@4805b000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x4805b000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio5";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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gpio6: gpio@4805d000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x4805d000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio6";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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gpio7: gpio@48051000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x48051000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio7";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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gpio8: gpio@48053000 {
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compatible = "ti,omap4-gpio";
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2012-10-23 10:37:09 +02:00
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reg = <0x48053000 0x200>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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2012-05-10 19:46:00 +05:30
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ti,hwmods = "gpio8";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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2013-03-07 15:44:39 -06:00
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#interrupt-cells = <2>;
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2012-05-10 19:46:00 +05:30
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};
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2013-02-22 15:33:31 -06:00
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gpmc: gpmc@50000000 {
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compatible = "ti,omap4430-gpmc";
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reg = <0x50000000 0x1000>;
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#address-cells = <2>;
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#size-cells = <1>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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2013-02-22 15:33:31 -06:00
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <4>;
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ti,hwmods = "gpmc";
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};
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2012-07-25 10:57:58 +05:30
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i2c1: i2c@48070000 {
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compatible = "ti,omap4-i2c";
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2012-10-23 10:37:10 +02:00
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reg = <0x48070000 0x100>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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2012-07-25 10:57:58 +05:30
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c1";
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};
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i2c2: i2c@48072000 {
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compatible = "ti,omap4-i2c";
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2012-10-23 10:37:10 +02:00
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reg = <0x48072000 0x100>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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2012-07-25 10:57:58 +05:30
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c2";
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};
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i2c3: i2c@48060000 {
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compatible = "ti,omap4-i2c";
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2012-10-23 10:37:10 +02:00
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reg = <0x48060000 0x100>;
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2013-05-31 14:32:57 +02:00
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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2012-07-25 10:57:58 +05:30
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#address-cells = <1>;
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#size-cells = <0>;
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ti,hwmods = "i2c3";
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};
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2012-10-23 10:37:10 +02:00
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i2c4: i2c@4807a000 {
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2012-07-25 10:57:58 +05:30
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compatible = "ti,omap4-i2c";
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2012-10-23 10:37:10 +02:00
|
|
|
reg = <0x4807a000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-25 10:57:58 +05:30
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c4";
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-23 10:37:10 +02:00
|
|
|
i2c5: i2c@4807c000 {
|
2012-07-25 10:57:58 +05:30
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 10:37:10 +02:00
|
|
|
reg = <0x4807c000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
|
2012-07-25 10:57:58 +05:30
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c5";
|
|
|
|
|
};
|
|
|
|
|
|
2013-10-10 16:15:34 -05:00
|
|
|
hwspinlock: spinlock@4a0f6000 {
|
|
|
|
|
compatible = "ti,omap4-hwspinlock";
|
|
|
|
|
reg = <0x4a0f6000 0x1000>;
|
|
|
|
|
ti,hwmods = "spinlock";
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-13 14:58:36 +05:30
|
|
|
mcspi1: spi@48098000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x48098000 0x200>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 14:58:36 +05:30
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi1";
|
|
|
|
|
ti,spi-num-cs = <4>;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 35>,
|
|
|
|
|
<&sdma 36>,
|
|
|
|
|
<&sdma 37>,
|
|
|
|
|
<&sdma 38>,
|
|
|
|
|
<&sdma 39>,
|
|
|
|
|
<&sdma 40>,
|
|
|
|
|
<&sdma 41>,
|
|
|
|
|
<&sdma 42>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1",
|
|
|
|
|
"tx2", "rx2", "tx3", "rx3";
|
2013-02-13 14:58:36 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi2: spi@4809a000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x4809a000 0x200>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 14:58:36 +05:30
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi2";
|
|
|
|
|
ti,spi-num-cs = <2>;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 43>,
|
|
|
|
|
<&sdma 44>,
|
|
|
|
|
<&sdma 45>,
|
|
|
|
|
<&sdma 46>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
2013-02-13 14:58:36 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi3: spi@480b8000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x480b8000 0x200>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 14:58:36 +05:30
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi3";
|
|
|
|
|
ti,spi-num-cs = <2>;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 15>, <&sdma 16>;
|
|
|
|
|
dma-names = "tx0", "rx0";
|
2013-02-13 14:58:36 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi4: spi@480ba000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x480ba000 0x200>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-13 14:58:36 +05:30
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi4";
|
|
|
|
|
ti,spi-num-cs = <1>;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 70>, <&sdma 71>;
|
|
|
|
|
dma-names = "tx0", "rx0";
|
2013-02-13 14:58:36 +05:30
|
|
|
};
|
|
|
|
|
|
2012-05-10 19:46:00 +05:30
|
|
|
uart1: serial@4806a000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 10:37:11 +02:00
|
|
|
reg = <0x4806a000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 19:46:00 +05:30
|
|
|
ti,hwmods = "uart1";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart2: serial@4806c000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 10:37:11 +02:00
|
|
|
reg = <0x4806c000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 19:46:00 +05:30
|
|
|
ti,hwmods = "uart2";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart3: serial@48020000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 10:37:11 +02:00
|
|
|
reg = <0x48020000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 19:46:00 +05:30
|
|
|
ti,hwmods = "uart3";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart4: serial@4806e000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 10:37:11 +02:00
|
|
|
reg = <0x4806e000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 19:46:00 +05:30
|
|
|
ti,hwmods = "uart4";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart5: serial@48066000 {
|
2012-10-23 10:37:11 +02:00
|
|
|
compatible = "ti,omap4-uart";
|
|
|
|
|
reg = <0x48066000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 19:46:00 +05:30
|
|
|
ti,hwmods = "uart5";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart6: serial@48068000 {
|
2012-10-23 10:37:11 +02:00
|
|
|
compatible = "ti,omap4-uart";
|
|
|
|
|
reg = <0x48068000 0x100>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
2012-05-10 19:46:00 +05:30
|
|
|
ti,hwmods = "uart6";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
2012-08-07 12:48:21 +05:30
|
|
|
|
|
|
|
|
mmc1: mmc@4809c000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 10:37:12 +02:00
|
|
|
reg = <0x4809c000 0x400>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 12:48:21 +05:30
|
|
|
ti,hwmods = "mmc1";
|
|
|
|
|
ti,dual-volt;
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 61>, <&sdma 62>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 12:48:21 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc2: mmc@480b4000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 10:37:12 +02:00
|
|
|
reg = <0x480b4000 0x400>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 12:48:21 +05:30
|
|
|
ti,hwmods = "mmc2";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 47>, <&sdma 48>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 12:48:21 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc3: mmc@480ad000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 10:37:12 +02:00
|
|
|
reg = <0x480ad000 0x400>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 12:48:21 +05:30
|
|
|
ti,hwmods = "mmc3";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 77>, <&sdma 78>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 12:48:21 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc4: mmc@480d1000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 10:37:12 +02:00
|
|
|
reg = <0x480d1000 0x400>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 12:48:21 +05:30
|
|
|
ti,hwmods = "mmc4";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 57>, <&sdma 58>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 12:48:21 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc5: mmc@480d5000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 10:37:12 +02:00
|
|
|
reg = <0x480d5000 0x400>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-07 12:48:21 +05:30
|
|
|
ti,hwmods = "mmc5";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 13:47:59 -05:00
|
|
|
dmas = <&sdma 59>, <&sdma 60>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 12:48:21 +05:30
|
|
|
};
|
2012-07-25 11:03:27 +05:30
|
|
|
|
|
|
|
|
keypad: keypad@4ae1c000 {
|
|
|
|
|
compatible = "ti,omap4-keypad";
|
2013-01-23 19:53:30 +05:30
|
|
|
reg = <0x4ae1c000 0x400>;
|
2012-07-25 11:03:27 +05:30
|
|
|
ti,hwmods = "kbd";
|
|
|
|
|
};
|
2012-08-29 16:31:04 +03:00
|
|
|
|
2012-08-29 16:31:07 +03:00
|
|
|
mcpdm: mcpdm@40132000 {
|
|
|
|
|
compatible = "ti,omap4-mcpdm";
|
|
|
|
|
reg = <0x40132000 0x7f>, /* MPU private access */
|
|
|
|
|
<0x49032000 0x7f>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 16:31:07 +03:00
|
|
|
ti,hwmods = "mcpdm";
|
2013-03-11 08:50:21 +01:00
|
|
|
dmas = <&sdma 65>,
|
|
|
|
|
<&sdma 66>;
|
|
|
|
|
dma-names = "up_link", "dn_link";
|
2012-08-29 16:31:07 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dmic: dmic@4012e000 {
|
|
|
|
|
compatible = "ti,omap4-dmic";
|
|
|
|
|
reg = <0x4012e000 0x7f>, /* MPU private access */
|
|
|
|
|
<0x4902e000 0x7f>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 16:31:07 +03:00
|
|
|
ti,hwmods = "dmic";
|
2013-03-11 08:50:21 +01:00
|
|
|
dmas = <&sdma 67>;
|
|
|
|
|
dma-names = "up_link";
|
2012-08-29 16:31:07 +03:00
|
|
|
};
|
|
|
|
|
|
2012-08-29 16:31:04 +03:00
|
|
|
mcbsp1: mcbsp@40122000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40122000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49022000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 16:31:04 +03:00
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp1";
|
2013-03-11 08:50:21 +01:00
|
|
|
dmas = <&sdma 33>,
|
|
|
|
|
<&sdma 34>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-29 16:31:04 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcbsp2: mcbsp@40124000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40124000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49024000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 16:31:04 +03:00
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp2";
|
2013-03-11 08:50:21 +01:00
|
|
|
dmas = <&sdma 17>,
|
|
|
|
|
<&sdma 18>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-29 16:31:04 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcbsp3: mcbsp@40126000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40126000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49026000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
2012-08-29 16:31:04 +03:00
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp3";
|
2013-03-11 08:50:21 +01:00
|
|
|
dmas = <&sdma 19>,
|
|
|
|
|
<&sdma 20>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-29 16:31:04 +03:00
|
|
|
};
|
2012-11-01 09:09:51 -05:00
|
|
|
|
|
|
|
|
timer1: timer@4ae18000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x4ae18000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer1";
|
|
|
|
|
ti,timer-alwon;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer2: timer@48032000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x48032000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer3: timer@48034000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x48034000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer3";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer4: timer@48036000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x48036000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer4";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer5: timer@40138000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x40138000 0x80>,
|
|
|
|
|
<0x49038000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer5";
|
|
|
|
|
ti,timer-dsp;
|
2013-04-17 18:23:15 -05:00
|
|
|
ti,timer-pwm;
|
2012-11-01 09:09:51 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer6: timer@4013a000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x4013a000 0x80>,
|
|
|
|
|
<0x4903a000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer6";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer7: timer@4013c000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x4013c000 0x80>,
|
|
|
|
|
<0x4903c000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer7";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer8: timer@4013e000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x4013e000 0x80>,
|
|
|
|
|
<0x4903e000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer8";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer9: timer@4803e000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x4803e000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer9";
|
2013-04-17 18:23:15 -05:00
|
|
|
ti,timer-pwm;
|
2012-11-01 09:09:51 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer10: timer@48086000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x48086000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer10";
|
2013-04-17 18:23:15 -05:00
|
|
|
ti,timer-pwm;
|
2012-11-01 09:09:51 -05:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer11: timer@48088000 {
|
2013-03-19 12:38:18 -05:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 09:09:51 -05:00
|
|
|
reg = <0x48088000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-01 09:09:51 -05:00
|
|
|
ti,hwmods = "timer11";
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
2012-11-05 18:22:51 +05:30
|
|
|
|
2013-02-27 11:54:45 +05:30
|
|
|
wdt2: wdt@4ae14000 {
|
|
|
|
|
compatible = "ti,omap5-wdt", "ti,omap3-wdt";
|
|
|
|
|
reg = <0x4ae14000 0x80>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
2013-02-27 11:54:45 +05:30
|
|
|
ti,hwmods = "wd_timer2";
|
|
|
|
|
};
|
|
|
|
|
|
2013-07-22 11:52:37 +01:00
|
|
|
emif1: emif@4c000000 {
|
2012-11-05 18:22:51 +05:30
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif1";
|
2013-10-15 12:37:50 +05:30
|
|
|
ti,no-idle-on-init;
|
2012-11-05 18:22:51 +05:30
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4c000000 0x400>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-05 18:22:51 +05:30
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
|
|
|
|
|
2013-07-22 11:52:37 +01:00
|
|
|
emif2: emif@4d000000 {
|
2012-11-05 18:22:51 +05:30
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif2";
|
2013-10-15 12:37:50 +05:30
|
|
|
ti,no-idle-on-init;
|
2012-11-05 18:22:51 +05:30
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4d000000 0x400>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
2012-11-05 18:22:51 +05:30
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
2013-03-07 19:05:17 +05:30
|
|
|
|
2013-10-03 18:12:37 +03:00
|
|
|
omap_control_usb2phy: control-phy@4a002300 {
|
|
|
|
|
compatible = "ti,control-phy-usb2";
|
|
|
|
|
reg = <0x4a002300 0x4>;
|
|
|
|
|
reg-names = "power";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
omap_control_usb3phy: control-phy@4a002370 {
|
|
|
|
|
compatible = "ti,control-phy-pipe3";
|
|
|
|
|
reg = <0x4a002370 0x4>;
|
|
|
|
|
reg-names = "power";
|
2013-03-07 19:05:17 +05:30
|
|
|
};
|
2013-03-07 19:05:18 +05:30
|
|
|
|
2013-08-21 20:01:32 +05:30
|
|
|
usb3: omap_dwc3@4a020000 {
|
2013-03-07 19:05:20 +05:30
|
|
|
compatible = "ti,dwc3";
|
|
|
|
|
ti,hwmods = "usb_otg_ss";
|
2013-08-21 20:01:30 +05:30
|
|
|
reg = <0x4a020000 0x10000>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
2013-03-07 19:05:20 +05:30
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
utmi-mode = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
dwc3@4a030000 {
|
2013-07-02 21:20:24 +03:00
|
|
|
compatible = "snps,dwc3";
|
2013-08-21 20:01:30 +05:30
|
|
|
reg = <0x4a030000 0x10000>;
|
2013-05-31 14:32:57 +02:00
|
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
2013-03-07 19:05:20 +05:30
|
|
|
usb-phy = <&usb2_phy>, <&usb3_phy>;
|
2013-10-10 16:19:54 +05:30
|
|
|
dr_mode = "peripheral";
|
2013-03-07 19:05:20 +05:30
|
|
|
tx-fifo-resize;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-08-21 20:01:31 +05:30
|
|
|
ocp2scp@4a080000 {
|
2013-03-07 19:05:18 +05:30
|
|
|
compatible = "ti,omap-ocp2scp";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
2013-08-21 20:01:31 +05:30
|
|
|
reg = <0x4a080000 0x20>;
|
2013-03-07 19:05:18 +05:30
|
|
|
ranges;
|
|
|
|
|
ti,hwmods = "ocp2scp1";
|
2013-03-07 19:05:19 +05:30
|
|
|
usb2_phy: usb2phy@4a084000 {
|
|
|
|
|
compatible = "ti,omap-usb2";
|
|
|
|
|
reg = <0x4a084000 0x7c>;
|
2013-10-03 18:12:37 +03:00
|
|
|
ctrl-module = <&omap_control_usb2phy>;
|
2013-03-07 19:05:19 +05:30
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb3_phy: usb3phy@4a084400 {
|
|
|
|
|
compatible = "ti,omap-usb3";
|
|
|
|
|
reg = <0x4a084400 0x80>,
|
|
|
|
|
<0x4a084800 0x64>,
|
|
|
|
|
<0x4a084c00 0x40>;
|
|
|
|
|
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
2013-10-03 18:12:37 +03:00
|
|
|
ctrl-module = <&omap_control_usb3phy>;
|
2013-03-07 19:05:19 +05:30
|
|
|
};
|
2013-03-07 19:05:18 +05:30
|
|
|
};
|
2013-06-07 18:52:48 +05:30
|
|
|
|
|
|
|
|
usbhstll: usbhstll@4a062000 {
|
|
|
|
|
compatible = "ti,usbhs-tll";
|
|
|
|
|
reg = <0x4a062000 0x1000>;
|
|
|
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
ti,hwmods = "usb_tll_hs";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbhshost: usbhshost@4a064000 {
|
|
|
|
|
compatible = "ti,usbhs-host";
|
|
|
|
|
reg = <0x4a064000 0x800>;
|
|
|
|
|
ti,hwmods = "usb_host_hs";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
|
|
|
|
|
usbhsohci: ohci@4a064800 {
|
|
|
|
|
compatible = "ti,ohci-omap3", "usb-ohci";
|
|
|
|
|
reg = <0x4a064800 0x400>;
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usbhsehci: ehci@4a064c00 {
|
|
|
|
|
compatible = "ti,ehci-omap", "usb-ehci";
|
|
|
|
|
reg = <0x4a064c00 0x400>;
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2013-06-18 22:36:38 -04:00
|
|
|
|
|
|
|
|
bandgap@4a0021e0 {
|
|
|
|
|
reg = <0x4a0021e0 0xc
|
|
|
|
|
0x4a00232c 0xc
|
|
|
|
|
0x4a002380 0x2c
|
|
|
|
|
0x4a0023C0 0x3c>;
|
|
|
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
|
compatible = "ti,omap5430-bandgap";
|
|
|
|
|
};
|
2012-05-10 19:46:00 +05:30
|
|
|
};
|
|
|
|
|
};
|
