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										 |  |  | #ifndef __ARCH_M68K_ATOMIC__
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							|  |  |  | #define __ARCH_M68K_ATOMIC__
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							|  |  |  | #include <linux/types.h>
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										 |  |  | #include <linux/irqflags.h>
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										 |  |  | #include <asm/cmpxchg.h>
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										 |  |  | #include <asm/barrier.h>
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							|  |  |  | /*
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							|  |  |  |  * Atomic operations that C can't guarantee us.  Useful for | 
					
						
							|  |  |  |  * resource counting etc.. | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | /*
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							|  |  |  |  * We do not have SMP m68k systems, so we don't have to deal with that. | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | #define ATOMIC_INIT(i)	{ (i) }
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										 |  |  | #define atomic_read(v)		ACCESS_ONCE((v)->counter)
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										 |  |  | #define atomic_set(v, i)	(((v)->counter) = i)
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							|  |  |  | /*
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							|  |  |  |  * The ColdFire parts cannot do some immediate to memory operations, | 
					
						
							|  |  |  |  * so for them we do not specify the "i" asm constraint. | 
					
						
							|  |  |  |  */ | 
					
						
							|  |  |  | #ifdef CONFIG_COLDFIRE
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							|  |  |  | #define	ASM_DI	"d"
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										 |  |  | #else
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										 |  |  | #define	ASM_DI	"di"
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										 |  |  | #endif
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										 |  |  | #define ATOMIC_OP(op, c_op, asm_op)					\
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							|  |  |  | static inline void atomic_##op(int i, atomic_t *v)			\ | 
					
						
							|  |  |  | {									\ | 
					
						
							|  |  |  | 	__asm__ __volatile__(#asm_op "l %1,%0" : "+m" (*v) : ASM_DI (i));\ | 
					
						
							|  |  |  | }									\ | 
					
						
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							|  |  |  | #ifdef CONFIG_RMW_INSNS
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							|  |  |  | #define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
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							|  |  |  | static inline int atomic_##op##_return(int i, atomic_t *v)		\ | 
					
						
							|  |  |  | {									\ | 
					
						
							|  |  |  | 	int t, tmp;							\ | 
					
						
							|  |  |  | 									\ | 
					
						
							|  |  |  | 	__asm__ __volatile__(						\ | 
					
						
							|  |  |  | 			"1:	movel %2,%1\n"				\ | 
					
						
							|  |  |  | 			"	" #asm_op "l %3,%1\n"			\ | 
					
						
							|  |  |  | 			"	casl %2,%1,%0\n"			\ | 
					
						
							|  |  |  | 			"	jne 1b"					\ | 
					
						
							|  |  |  | 			: "+m" (*v), "=&d" (t), "=&d" (tmp)		\ | 
					
						
							|  |  |  | 			: "g" (i), "2" (atomic_read(v)));		\ | 
					
						
							|  |  |  | 	return t;							\ | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | #else
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							|  |  |  | #define ATOMIC_OP_RETURN(op, c_op, asm_op)				\
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							|  |  |  | static inline int atomic_##op##_return(int i, atomic_t * v)		\ | 
					
						
							|  |  |  | {									\ | 
					
						
							|  |  |  | 	unsigned long flags;						\ | 
					
						
							|  |  |  | 	int t;								\ | 
					
						
							|  |  |  | 									\ | 
					
						
							|  |  |  | 	local_irq_save(flags);						\ | 
					
						
							|  |  |  | 	t = (v->counter c_op i);					\ | 
					
						
							|  |  |  | 	local_irq_restore(flags);					\ | 
					
						
							|  |  |  | 									\ | 
					
						
							|  |  |  | 	return t;							\ | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | #endif /* CONFIG_RMW_INSNS */
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							|  |  |  | #define ATOMIC_OPS(op, c_op, asm_op)					\
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							|  |  |  | 	ATOMIC_OP(op, c_op, asm_op)					\ | 
					
						
							|  |  |  | 	ATOMIC_OP_RETURN(op, c_op, asm_op) | 
					
						
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							|  |  |  | ATOMIC_OPS(add, +=, add) | 
					
						
							|  |  |  | ATOMIC_OPS(sub, -=, sub) | 
					
						
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							|  |  |  | #undef ATOMIC_OPS
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							|  |  |  | #undef ATOMIC_OP_RETURN
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							|  |  |  | #undef ATOMIC_OP
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										 |  |  | static inline void atomic_inc(atomic_t *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	__asm__ __volatile__("addql #1,%0" : "+m" (*v)); | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | static inline void atomic_dec(atomic_t *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	__asm__ __volatile__("subql #1,%0" : "+m" (*v)); | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | static inline int atomic_dec_and_test(atomic_t *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	char c; | 
					
						
							|  |  |  | 	__asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | 
					
						
							|  |  |  | 	return c != 0; | 
					
						
							|  |  |  | } | 
					
						
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										 |  |  | static inline int atomic_dec_and_test_lt(atomic_t *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	char c; | 
					
						
							|  |  |  | 	__asm__ __volatile__( | 
					
						
							|  |  |  | 		"subql #1,%1; slt %0" | 
					
						
							|  |  |  | 		: "=d" (c), "=m" (*v) | 
					
						
							|  |  |  | 		: "m" (*v)); | 
					
						
							|  |  |  | 	return c != 0; | 
					
						
							|  |  |  | } | 
					
						
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										 |  |  | static inline int atomic_inc_and_test(atomic_t *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	char c; | 
					
						
							|  |  |  | 	__asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); | 
					
						
							|  |  |  | 	return c != 0; | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | #ifdef CONFIG_RMW_INSNS
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							|  |  |  | #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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							|  |  |  | #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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							|  |  |  | #else /* !CONFIG_RMW_INSNS */
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							|  |  |  | static inline int atomic_cmpxchg(atomic_t *v, int old, int new) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	unsigned long flags; | 
					
						
							|  |  |  | 	int prev; | 
					
						
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							|  |  |  | 	local_irq_save(flags); | 
					
						
							|  |  |  | 	prev = atomic_read(v); | 
					
						
							|  |  |  | 	if (prev == old) | 
					
						
							|  |  |  | 		atomic_set(v, new); | 
					
						
							|  |  |  | 	local_irq_restore(flags); | 
					
						
							|  |  |  | 	return prev; | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | static inline int atomic_xchg(atomic_t *v, int new) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	unsigned long flags; | 
					
						
							|  |  |  | 	int prev; | 
					
						
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							|  |  |  | 	local_irq_save(flags); | 
					
						
							|  |  |  | 	prev = atomic_read(v); | 
					
						
							|  |  |  | 	atomic_set(v, new); | 
					
						
							|  |  |  | 	local_irq_restore(flags); | 
					
						
							|  |  |  | 	return prev; | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | #endif /* !CONFIG_RMW_INSNS */
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							|  |  |  | #define atomic_dec_return(v)	atomic_sub_return(1, (v))
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							|  |  |  | #define atomic_inc_return(v)	atomic_add_return(1, (v))
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							|  |  |  | static inline int atomic_sub_and_test(int i, atomic_t *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	char c; | 
					
						
							|  |  |  | 	__asm__ __volatile__("subl %2,%1; seq %0" | 
					
						
							|  |  |  | 			     : "=d" (c), "+m" (*v) | 
					
						
							|  |  |  | 			     : ASM_DI (i)); | 
					
						
							|  |  |  | 	return c != 0; | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | static inline int atomic_add_negative(int i, atomic_t *v) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	char c; | 
					
						
							|  |  |  | 	__asm__ __volatile__("addl %2,%1; smi %0" | 
					
						
							|  |  |  | 			     : "=d" (c), "+m" (*v) | 
					
						
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										 |  |  | 			     : ASM_DI (i)); | 
					
						
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										 |  |  | 	return c != 0; | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | static inline void atomic_clear_mask(unsigned long mask, unsigned long *v) | 
					
						
							|  |  |  | { | 
					
						
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										 |  |  | 	__asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask))); | 
					
						
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										 |  |  | } | 
					
						
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							|  |  |  | static inline void atomic_set_mask(unsigned long mask, unsigned long *v) | 
					
						
							|  |  |  | { | 
					
						
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										 |  |  | 	__asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask)); | 
					
						
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										 |  |  | } | 
					
						
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										 |  |  | static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u) | 
					
						
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										 |  |  | { | 
					
						
							|  |  |  | 	int c, old; | 
					
						
							|  |  |  | 	c = atomic_read(v); | 
					
						
							|  |  |  | 	for (;;) { | 
					
						
							|  |  |  | 		if (unlikely(c == (u))) | 
					
						
							|  |  |  | 			break; | 
					
						
							|  |  |  | 		old = atomic_cmpxchg((v), c, c + (a)); | 
					
						
							|  |  |  | 		if (likely(old == c)) | 
					
						
							|  |  |  | 			break; | 
					
						
							|  |  |  | 		c = old; | 
					
						
							|  |  |  | 	} | 
					
						
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										 |  |  | 	return c; | 
					
						
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										 |  |  | } | 
					
						
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							|  |  |  | #endif /* __ARCH_M68K_ATOMIC __ */
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