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											2008-05-19 16:53:02 -07:00
										 |  |  | /*
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											2005-04-16 15:20:36 -07:00
										 |  |  |  * tsunami.h:  Module specific definitions for Tsunami V8 Sparcs | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | #ifndef _SPARC_TSUNAMI_H
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							|  |  |  | #define _SPARC_TSUNAMI_H
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							|  |  |  | #include <asm/asi.h>
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							|  |  |  | 
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							|  |  |  | /* The MMU control register on the Tsunami:
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							|  |  |  |  * | 
					
						
							|  |  |  |  * ----------------------------------------------------------------------- | 
					
						
							|  |  |  |  * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME| | 
					
						
							|  |  |  |  * ----------------------------------------------------------------------- | 
					
						
							|  |  |  |  *  31      24 23 22 21 20 19-18 17  16 14  13-12 11 10-9  8  7 6-2  1  0 | 
					
						
							|  |  |  |  * | 
					
						
							|  |  |  |  * SW: Enable Software Table Walks  0=off 1=on | 
					
						
							|  |  |  |  * AV: Address View bit | 
					
						
							|  |  |  |  * DV: Data View bit | 
					
						
							|  |  |  |  * MV: Memory View bit | 
					
						
							|  |  |  |  * PC: Parity Control | 
					
						
							|  |  |  |  * ITD: ITBR disable | 
					
						
							|  |  |  |  * ALC: Alternate Cacheable | 
					
						
							|  |  |  |  * PE: Parity Enable   0=off 1=on | 
					
						
							|  |  |  |  * RC: Refresh Control | 
					
						
							|  |  |  |  * IE: Instruction cache Enable  0=off 1=on | 
					
						
							|  |  |  |  * DE: Data cache Enable  0=off 1=on | 
					
						
							|  |  |  |  * NF: No Fault, same as all other SRMMUs | 
					
						
							|  |  |  |  * ME: MMU Enable, same as all other SRMMUs | 
					
						
							|  |  |  |  */ | 
					
						
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							|  |  |  | #define TSUNAMI_SW        0x00800000
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							|  |  |  | #define TSUNAMI_AV        0x00400000
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							|  |  |  | #define TSUNAMI_DV        0x00200000
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							|  |  |  | #define TSUNAMI_MV        0x00100000
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							|  |  |  | #define TSUNAMI_PC        0x00020000
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							|  |  |  | #define TSUNAMI_ITD       0x00010000
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							|  |  |  | #define TSUNAMI_ALC       0x00008000
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							|  |  |  | #define TSUNAMI_PE        0x00001000
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							|  |  |  | #define TSUNAMI_RCMASK    0x00000C00
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							|  |  |  | #define TSUNAMI_IENAB     0x00000200
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							|  |  |  | #define TSUNAMI_DENAB     0x00000100
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							|  |  |  | #define TSUNAMI_NF        0x00000002
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							|  |  |  | #define TSUNAMI_ME        0x00000001
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							|  |  |  | static inline void tsunami_flush_icache(void) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" | 
					
						
							|  |  |  | 			     : /* no outputs */ | 
					
						
							|  |  |  | 			     : "i" (ASI_M_IC_FLCLEAR) | 
					
						
							|  |  |  | 			     : "memory"); | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | static inline void tsunami_flush_dcache(void) | 
					
						
							|  |  |  | { | 
					
						
							|  |  |  | 	__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" | 
					
						
							|  |  |  | 			     : /* no outputs */ | 
					
						
							|  |  |  | 			     : "i" (ASI_M_DC_FLCLEAR) | 
					
						
							|  |  |  | 			     : "memory"); | 
					
						
							|  |  |  | } | 
					
						
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							|  |  |  | #endif /* !(_SPARC_TSUNAMI_H) */
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